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Allinea to Share Top Tips for Code Modernization at XSEDE16

Today, Allinea announced that the company will be exhibiting at XSEDE16 July 17-21 in Miami. The conference will attract an audience across industry and academia to discuss the key themes of diversity, big data and science at scale. “Our tools are used extensively across the XSEDE user base so we’re delighted to be extending the value they bring by giving practical advice for getting the best out of infrastructure capabilities through software tuning, especially given the addition of support for the full Intel Xeon Phi family in our new v6.1 software release,” said Rob Rick, VP Americas for Allinea.”

Allinea Programming Releases Tools for Intel Xeon Phi Processor

“Our latest product enhancements will solidify our customers’ investment in the next generation Intel Xeon Phi processor,” said Mark O’Connor, VP Product Management at Allinea. “Knights Landing’ has the potential to unleash new capabilities for HPC code users and our new release brings a powerful debugger, profiler and performance reports for tackling the essential preparatory work needed to optimize legacy code and realize the processor’s true potential for reducing software run times.”

Allinea Tools to Power NEC Supercomputer at VSC in Belgium

The Flemish Supercomputer Center (VSC) is planning the deployment of a new NEC cluster that will represent Belgium’s largest investment in HPC to date. To help VSC unleash the potential of the system, Allinea software tools will be used to speed up code performance. “We are delighted to be supporting VSC in providing better education to its users around code efficiency,” said David Lecomber, CEO and Founder of Allinea. “The fact of the matter is, without visibility of code performance, researchers cannot get the full value from HPC. By appreciating how their code makes a difference to project delivery, researchers can achieve more for less cost. By underlining this best practice, VSC’s approach is one that is refreshing and makes great economic sense.”

Interview: Cavium to Move ARM Forward for HPC at ISC 2016

“Cavium ThunderX has significant differentiation in the 64-bit ARM market as Cavium is the first ARMv8 vendor to deliver dual socket support with full ARMv8.1 implementation and significant advantage in CPU cores with 48 cores per socket. In addition, ThunderX supports large memory capacity (512GB per socket, 1TB in a 2S system) with excellent memory bandwidth and low memory latency. In addition, ThunderX includes multiple 10 GbE / 40GbE network interfaces delivering excellent IO throughput. These features enable ThunderX to deliver the core performance & scale out capability that the HPC market requires.”

Allinea Speeds Tomorrow’s Meteorological Code

Allinea Software reports that the company is helping weather and climate researchers to adapt advanced weather models to better exploit today’s technology capability and get ready for future platforms. The company will address leading climatologists and meteorologists on best practices for scalable code development April 6-7 at the 4th ENES HPC Workshop. The session will reference the application of Allinea’s tools across over 20 weather and climate customers worldwide.

Code Modernization for Smarter Geophysics

Today Allinea announced plans to champion what it sees as a key survival message for the Energy industry when it exhibits at the Rice Oil and Gas HPC Conference in Houston next week. “We’ll be underlining to geophysicists at the conference the real commercial gains to be had from focusing on code performance,” said Robert Rick, Allinea’s VP of Sales, Americas. “HPC is helping the industry to operate more efficiently. The next step is for this market is to use code optimization to speed up the valuable seismic imaging and reservoir modeling processes, which are now essential to this industry.”

ExaNeSt European Consortium to Develop Exascale Architecture

In this special guest feature, Robert Roe from Scientific Computing World reports that a new Exascale computing architecture using ARM processors is being developed by a European consortium of hardware and software providers, research centers, and industry partners. Funded by the European Union’s Horizon2020 research program, a full prototype of the new system is expected to be ready by 2018.

European ExaNeSt Project to Pave the Way to Exascale

Today the European Consortium announced a step towards Exascale computing with the ExaNeSt project. Funded by the Horizon 2020 initiative, ExaNeSt plans to build its first straw man prototype in 2016. The Consortium consists of twelve partners, each of which has expertise in a core technology needed for innovation to reach Exascale. ExaNeSt takes the sensible, integrated approach of co-designing the hardware and software, enabling the prototype to run real-life evaluations, facilitating its scalability and maturity into this decade and beyond.

Allinea Scalable Profiler Speeds Application Readiness for Summit Supercomputer at Oak Ridge

Today Allinea announced that Oak Ridge National Laboratory has deployed its code performance profiler Allinea MAP in strength on the Titan supercomputer. Allinea MAP enables developers of software for supercomputers of all sizes to produce faster code. Its deployment on Titan will help to use the system’s 299,008 CPU cores and 18,688 GPUs more efficiently. Software teams at Oak Ridge are also preparing for the arrival of the next generation supercomputer, the Summit pre-Exascale system – which will be capable of over 150 PetaFLOPS in 2018.

Allinea Tools Help Deliver 30% Performance Boost in Reservoir Simulation

Today Allinea reports that developers of Roxar Software Solutions at Emerson Process Management used the Allinea Forge to increase the performance of their Tempest MORE next-generation reservoir simulator by 30 percent.