In this video from the 2016 HPC User Forum in Austin, a select panel of HPC vendors describe their disruptive technologies for high performance computing. Vendors include: Altair, SUSE, ARM, AMD, Ryft, Red Hat, Cray, and Hewlett Packard Enterprise. “A disruptive innovation is an innovation that creates a new market and value network and eventually disrupts an existing market and value network, displacing established market leading firms, products and alliances.”
Yutaka Ishikawa from Riken AICS presented this talk at the HPC User Forum. “Slated for delivery sometime around 2022, the ARM-based Post-K Computer has a performance target of being 100 times faster than the original K computer within a power envelope that will only be 3-4 times that of its predecessor. RIKEN AICS has been appointed as the main organization for leading the development of the Post-K.”
This week at the Hot Chips conference, Phytium Technology from China unveiled a 64-core CPU and a related prototype computer server. “Phytium says the new CPU chip, with 64-bit arithmetic compatible with ARMv8 instructions, is able to perform 512 GFLOPS at base frequency of 2.0 GHz and on 100 watts of power dissipation.”
The Fujitsu Journal has posted details on a recent Hot Chips presentation by Toshio Yoshida about the instruction set architecture (ISA) of the Post-K processor. “The Post-K processor employs the ARM ISA, developed by ARM Ltd., with enhancements for supercomputer use. Meanwhile, Fujitsu has been developing the microarchitecture of the processor. In Fujitsu’s presentation, we also explained that our development of mainframe processors and UNIX server SPARC processors will continue into the future. The reason that Fujitsu is able to continuously develop multiple processors is our shared microarchitecture approach to processor development.”
Over at the ARM Community Blog, Nigel Stephens writes that the company has introduced scalable vector extensions (SVE) their A64 instruction set to bolster high performance computing. Fujitsu is developing a new HPC processor conforming to ARMv8-A with SVE for the Post-K computer.
In this podcast, the Radio Free HPC team welcomes Shahin Khan from OrionX to a discussion on chip architectures for HPC. “More and more new alternative architectures were in evidence at ISC in Germany this year, but what does it take for a chip architecture to be a winner? Looking back, chips like DEC Alpha had many advantages over the competition, but it did not survive.”
The Heterogeneous System Architecture (HSA) Foundation has released the HSA 1.1 specification, significantly enhancing the ability to integrate open and proprietary IP blocks in heterogeneous designs. The new specification is the first to define the interfaces that enable IP blocks from different vendors to communicate, interoperate and collectively compose an HSA system.
Today Mellanox announced the BlueField family of programmable processors for networking and storage applications. “As a networking offload co-processor, BlueField will complement the host processor by performing wire-speed packet processing in-line with the network I/O, freeing the host processor to deliver more virtual networking functions (VNFs),” said Linley Gwennap, principal analyst at the Linley Group. “Network offload results in better rack density, lower overall power consumption, and deterministic networking performance.”
“Just as representative benchmarks like HPCG are set to replace Linpack, so a focus on software is taking over. From industry analysts to users at SC15 we heard that software is the number one challenge and the number one opportunity to have world-class impact.”
The OpenACC Standards Group released the 2.5 version of the OpenACC API specification.