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Taming Heterogeneity in HPC – The DEEP-ER take

Norbert Eicker from the Jülich Supercomputing Centre presented this talk at the SAI Computing Conference in London. “The ultimate goal is to reduce the burden on the application developers. To this end DEEP/-ER provides a well-accustomed programming environment that saves application developers from some of the tedious and often costly code modernization work. Confining this work to code-annotation as proposed by DEEP/-ER is a major advancement.”

EXTOLL Network Chip Enables Network-attached Accelerators

Today EXTOLL in Germany released its new TOURMALET high-performance network chip for HPC. “The key demands of HPC are high bandwidth, low latency, and high message rates. The TOURMALET PCI-Express gen3 x16 board shows an MPI latency of 850ns and a message rate of 75M messages per second. The message rate value is CPU-limited, while TOURMALET is designed for well above 100M msg/s.”

How Intel Worked with the DEEP Consortium to Challenge Amdahl’s Law

Funded by the European Commission in 2011, the DEEP project was the brainchild of scientists and researchers at the Jülich Supercomputing Centre (JSC) in Germany. The basic idea is to overcome the limitations of standard HPC systems by building a new type of heterogeneous architecture. One that could dynamically divide less parallel and highly parallel parts of a workload between a general-purpose Cluster and a Booster—an autonomous cluster with Intel® Xeon Phi™ processors designed to dramatically improve performance of highly parallel code.

EXTOLL Deploys Immersion Cooled Compute Booster at Jülich

Today Extoll, the German HPC innovation company, announced that is has it has successfully implemented its new GreenICE immersion cooling system at the Jülich Supercomputing Centre. As part of the DEEP Dynamical Exascale Entry Platform project, GreenICE was developed to meet the need for increased compute power, density, and energy efficiency.

DEEP Project Unveils 500 Teraflop Prototype

The EU-funded DEEP Project has unveiled their innovative HPC platform: a 500 TFlop/s prototype system that implements a Cluster-Booster concept that has a lot in common with a turbocharged engine. The prototype operates with a full system software stack and programming environment engineered for performance and ease of use.

EXTOLL Rolls Out TOURMALET Network Chip at ISC 2015

Last week at ISC 2015, EXTOLL from Germany introduced its TOURMALET 100G network chip and PCIe Board.

Interview: Behind the Scenes at the DEEP Project

“In terms of the hardware, one of the biggest successes surely was to make the Intel Xeon Phi boot via the Extoll network. This might not sound so special, but for the DEEP project it is – because this basically is the essential milestone for proving our architectural concept: The Cluster-Booster approach. In traditional heterogeneous architectures the accelerators cannot boot without a host CPU. Our aim was to develop a cluster – made up of usual CPUs – and a booster – made up of accelerators – that can both act autonomously while being interconnected via two networks.”