Applications for the DEEP and DEEP-ER Projects


“To evaluate the DEEP concept and to prove its programmability, selected applications are ported to the DEEP system. They serve to test the system, to compare its performance with respect to standard architectures, and even to propose improvements to the system’s hardware and software.”

New Energy Optimization Tools from Allinea at ISC’14

James Reinders

In this video from ISC’14, James Reinders from Intel and Patrick Wohlschlägel from Allinea discuss new energy optimization programming tools from Allinea Software. “Our developer-centric tool, Allinea MAP, will allow scientific code developers to focus energy optimization down into the source code — making changes to the application to drive faster performance and lower energy consumption at the same time.”

Intel Enterprise Edition for Lustre Software at ISC’14

Brent Gorda, Intel

“The Intel Enterprise Edition for Lustre software unleashes the performance and scalability of the Lustre parallel file system for HPC workloads, including technical ‘big data’ applications common within today’s enterprises. It allows end-users that need the benefits of large–scale, high bandwidth storage to tap the power and scalability of Lustre, with the simplified installation, configuration, and management features provided by Intel Manager for Lustre software, a management solution purpose-built by the Lustre experts at Intel for the Lustre file system.”

Computational Biology using Intel Xeon and Intel Xeon Phi


In this video from ISC’14, Christian Blau from the Max Planck Institute and Greg Johnson from Intel describe their demonstration of Computational Biology using Intel Xeon and Intel Xeon Phi.

Video: DEEP and DEEP-ER Project Updates at ISC’14


In this video from ISC’14, the DEEP and DEEP-ER Project teams describe their prototype hardware and software. “The DEEP consortium will develop a novel, Exascale-enabling supercomputing architecture with a matching SW stack and a set of optimized grand-challenge simulation applications. DEEP takes the concept of compute acceleration to a new level: instead of adding accelerator cards to Cluster nodes, an accelerator Cluster, called Booster, will complement a conventional HPC system and increase its compute performance.”

Video: PRACE Award Winners – Sustained Petascale Seismic Simulations


In this video from ISC’14, Alex Heinecke from Intel and Sebastian Rettenberger from the Technical University of Munich describe their award-winning paper on volcano simulation. “Seismic simulations in realistic 3D Earth models require peta- or even exascale compute power to capture small-scale features of high relevance for scientific and industrial applications. In this paper, we present optimizations of SeisSol — a seismic wave propagation solver based on the Arbitrary high-order accurate DERivative (ADER) Discontinuous Galerkin method on fully adaptive, unstructured tetrahedral meshes — to run simulations under production conditions at petascale performance.”

Slidecast: Micron HMC Memory Technology to Enhance Knights Landing


In this slidecast, Mike Black from Micron describes the company’s Hybrid Memory Cube technology for the next-generation Xeon Phi processor, codenamed Knights Landing. “Delivering 5X the sustained memory bandwidth versus DDR4 with one-third the energy per bit in half the footprint, the Knights Landing high performance, on package memory combines high-speed logic and DRAM layers into one optimized package that will set a new industry benchmark for performance and energy efficiency.”

Interview: Xcelerit Partners with Intel to Accelerate Code in Supercomputing

Hicham Lahlou

“Our core product is the Xcelerit SDK, a Software Development Kit that makes it easy for domain specialists (i.e. mathematicians in banks or geophysicists in energy exploration firms) to convert their existing code to take advantage of multi-core, GPU and other hardware accelerators.”

Podcast: Fabric Integration is Coming to Intel True Scale

Joe Yaworski

“With Fabric Integration, you pick up five value vectors. One is an in increase in performance; so the closer you can drive the fabric to the CPU, the more things you can do to increase the overall performance of both the CPU, and the fabric together. Number two, you pick up density. Because now you’re not taking up any board space or PCIe slots and things like that. Number three, you pick up also the options for improved value, in terms of price per performance. Number four, you reduce power. And number five, by getting rid of things like the PCIe bus, you reduce componentry – which again reduces power – as well as improves reliability.”

Intel’s True Scale Fabric Gains Momentum; Forty Percent Growth from Last Year

Joe Yaworski

“We really need to re-look at what the requirements are that will lead us all the way up to being able to support Exascale deployments. One of these absolute requirements is CPU fabric integration, because the performance that’s needed, the density, the power, are all areas that have to be vastly improved to support deployments of exascale.”