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Coral and Intel’s Scalable System Framework – The Path to Exascale

mark

“HPC has reached an inflection point with the convergence of traditional high performance computing and the emerging world of Big Data analytics. Intel’s HPC Scalable System Framework enables an unprecedented level of system balance, performance, and scalability necessary to meet the demands of bot compute- and data-intensive workloads, today and well into the future.”

Nested Parallelism

phi-compressor

The benefits of nested parallelism on highly threaded applications can be determined and quantified. With the number of cores in both the host CPU (Intel Xeon) and the coprocessor (Intel Xeon Phi) continues to increase, much thought must be given to minimizing the thread overhead when many threads need to be synchronized, as well as the memory access for each processor (core). Tasks that can be spread across an entire system to exploit the algorithm’s parallelism, should be mapped to the NUMA node to make them more efficient.

Quantum Chemistry at Scale

quantum chemistry

“Applications can be tuned to use both the Intel Xeon and the Intel Xeon Phi simultaneously, without modifying the code to just run on the coprocessor. Using a number of software tools from Intel, performance of a coupled cluster method can be demonstrated to gain a tremendous performance with excellent scaling.”

TACC to Acquire Cray XC40 Supercomputer

cray

Today Cray announced the Company has been awarded a contract to provide a Cray XC40 supercomputer to the Texas Advanced Computing Center (TACC). This contract marks the first ever Cray supercomputer to be installed at TACC.

Integrating an Intel Xeon Phi Cluster

Cray_Computer_Cluster_05_HRSS

At the National Institute of Computational Sciences (NICS), a joint venture by the University of Tennessee and the Oak Ridge National Laboratory, a joint team set out to learn how to integrate the Intel Xeon Phi coprocessor into cluster configurations.

Power Usage for Coprocessors

PS5666X

“As the use of coprocessors increases to speedup HPC applications, it is important to understand how much additional power the coprocessors use. With various measurements and benchmarks arising to calculate the power used during the running of compute and data intensive applications, measuring the power draw from an Intel Xeon Phi coprocessor is important to understanding the best use of resources.”

Computing With MPI in Heterogeneous Environments

Stampede

Designating the appropriate provider for large MPI applications is critical to taking advantage of all of the compute power available. “A modern HPC system with multiple host cpus and multiple coprocessors such as the Intel Xeon Phi coprocessor housed in numerous racks can be optimized for maximum application performance with intelligent thread placement.”

Concurrent Kernel Offloading

phi

“The combination of using a host cpu such as an Intel Xeon combined with a dedicated coprocessor such as the Intel Xeon Phi coprocessor has been shown in many cases to improve the performance of an application by significant amounts. When the datasets are large enough, it makes sense to offload as much of the workload as possible. But is this the case when the potential offload data sets are not as large?”

Why Hardware is Leaving Software Behind

pracedays1

In the first report from last week’s PRACEdays15 conference in Dublin, Tom Wilkie from Scientific Computing World considers why so much Exascale software will be open source and why engineers are not using parallel programs.

Load Balancing Using OpenMP 4.0

OpenMP

OpenMP 4.0 standard now allows for the offloading of portions of the application, in order to take more advantage of many-core accelerators such as the Intel Xeon Phi coprocessor.