Intel Adds Vector Instructions for Knights Landing

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James Reinders writes that additional vector instructions have now been documented for Intel AVX-512, which will be first implemented in the future Intel Xeon Phi processor and coprocessor known by the code name Knights Landing.

Farber to Teach All-Day Tutorial At SC14

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Over at TechEnablement, Rob Farber writes that he will be teaching an all-day tutorial “From ‘Hello World’ to Exascale Using x86, GPUs and Intel Xeon Phi Coprocessors” (tut106s1) at SC14 in New Orleans. The tutorial takes place on Sunday November 16, 2014.

Job of the Week: Xeon Phi Platform Marketing Engineer at Intel

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Intel is seeking an Xeon Phi Platform Marketing Engineer in our Job of the Week.

Computational Biology using Intel Xeon and Intel Xeon Phi

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In this video from ISC’14, Christian Blau from the Max Planck Institute and Greg Johnson from Intel describe their demonstration of Computational Biology using Intel Xeon and Intel Xeon Phi.

Video: PRACE Award Winners – Sustained Petascale Seismic Simulations

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In this video from ISC’14, Alex Heinecke from Intel and Sebastian Rettenberger from the Technical University of Munich describe their award-winning paper on volcano simulation. “Seismic simulations in realistic 3D Earth models require peta- or even exascale compute power to capture small-scale features of high relevance for scientific and industrial applications. In this paper, we present optimizations of SeisSol — a seismic wave propagation solver based on the Arbitrary high-order accurate DERivative (ADER) Discontinuous Galerkin method on fully adaptive, unstructured tetrahedral meshes — to run simulations under production conditions at petascale performance.”

RSC Announces Record Compute Density with Xeon Phi at ISC’14

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Russian supercomputing vendor RSC Group announced world record compute and power density with their RSC PetaStream and RSC Tornado based clusters.

Video: Intel Unveils Knights Landing Details at ISC’14

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In the course of this talk, Intel’s Raj Hazra unveils details of the Knights Landing architecture including the new Omni Scale Fabric, an integrated, high performance interconnect designed for CPU to CPU communications. “The industry ecosystem needs to work together to tackle challenges in system architecture, programming models, and energy efficiency – all while lowering the thresholds for broader user access and usability.”

Slidecast: Micron HMC Memory Technology to Enhance Knights Landing

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In this slidecast, Mike Black from Micron describes the company’s Hybrid Memory Cube technology for the next-generation Xeon Phi processor, codenamed Knights Landing. “Delivering 5X the sustained memory bandwidth versus DDR4 with one-third the energy per bit in half the footprint, the Knights Landing high performance, on package memory combines high-speed logic and DRAM layers into one optimized package that will set a new industry benchmark for performance and energy efficiency.”

Job of the Week: HPC Fabric Management Software Engineer at Intel

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Intel is seeking an HPC Fabric Management Software Engineer in our Job of the Week.

New Paper: Cluster-Level Tuning of a Shallow Water Equation Solver on the Intel MIC Architecture

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Colfax Research has published a new white paper entitled “Cluster-Level Tuning of a Shallow Water Equation Solver on the Intel MIC Architecture.” Written by Andrey Vladimirov, the paper demonstrates the optimization of the execution environment of a hybrid OpenMP+MPI computational fluid dynamics code (shallow water equation solver) on a cluster enabled with Intel Xeon Phi coprocessors.