I’m on my way home from a series of Springtime HPC conferences with boatload of new videos and interviews on the latest in high performance computing. Here are some notable items that may have not made it to the front page.
“As we see Moore’s Law alive and well, more and more parallelism is introduced into all computing platforms and on all levels of integration and programming to achieve higher performance and energy efficiency. We will discuss Multi- and Many-Core solutions for highly parallel workloads with general purpose and energy efficient technologies. We will also touch on the challenges and opportunities for parallel programming models, methodologies and software tools to achieve highly efficient and highly productive parallel applications. At the end we will take a brief look towards Exascale computing.”
“This talk will focus on programming models and their designs for upcoming exascale systems with millions of processors and accelerators. Current status and future trends of MPI and PGAS (UPC and OpenSHMEM) programming models will be presented. We will discuss challenges in designing runtime environments for these programming models by taking into account support for multi-core, high-performance networks, GPGPUs, Intel MIC, scalable collectives (multi-core-aware, topology-aware, and power-aware), non-blocking collectives using Offload framework, one-sided RMA operations, schemes and architectures for fault-tolerance/fault-resilience.”
In this video from the 2015 OFS Developer’s Workshop, Katie Antypas from LBNL describes preparations for the Cori supercomputer. “We need to emphasize here that the Knights Landing processor is self-hosted, and so that means it’s not an accelerator. It’s not a coprocessor and the particular kernel processor that will be having for NERSC-8, will have more than 60 cores and it will have multiple hardware threads for the core. That’s a lot, right? Having 60 cores per node with multiple hardware threads. That a significant increase from both our Hopper and Edison system, which has 24 cores each.”
“This talk includes an overview of the present and future of the Intel Many Integrated Core architecture. I will illustrate the value proposition of Intel Xeon Phi coprocessors for scientific applications with case studies done at Colfax. Original training program will be featured, designed to help developers to get started with the MIC architecture.”
The University of Cambridge plans to transition their HPC workloads to Intel’s Xeon Phi co-processors. The deal will see Intel work along with Dell staff to upgrade the high performance infrastructure used to serve research departments within the university, working in areas such as genomics and astronomy, as well as a growing number of businesses with large compute demands.
The University of Houston (UH) is adding a new, state-of-the-art supercomputer to its arsenal of research tools. With 1860 compute cores, the new Opuntia cluster will be used primarily for scientific and engineering work. The acquisition of this new system marks the start of a new era of supercomputing not only for the University of […]