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Fujitsu Starts of Operations for Japan’s Fastest Supercomputer

Today Fujitsu today announced the completion of the Oakforest-PACS supercomputer at the Joint Center for Advanced High Performance Computing (JCAHPC), which is jointly run by the University of Tokyo and the University of Tsukuba, and that operations have commenced today. This new supercomputer is comprised of FUJITSU Server PRIMERGY CX600 M1 x86 servers. It uses […]

Intel Xeon Phi with Software Defined Visualization at SC16

“Software Defined Visualization (SDVis) is an open source initiative from Intel and industry collaborators to improve the visual fidelity, performance and efficiency of prominent visualization solutions – with a particular emphasis on supporting the rapidly growing “Big Data” usage on workstations through HPC supercomputing clusters without the memory limitations and cost of GPU based solutions. Existing applications can be enhanced using the high performing parallel software rendering libraries OpenSWR, Embree, and OSPRay. At the Intel HPC Developer Conference, Amstutz provided an introduction to this initiative, its benefits, a brief descriptions of accomplishments in the past year and talk about the changes made to Intel provided libraries in the past year.”

Cray Sets New Supercomputing Record with HLRS and Ansys

ANSYS, HLRS and Cray have pushed the boundaries of supercomputing by achieving a new supercomputing milestone by scaling ANSYS software to 172,032 cores on the Cray XC40 supercomputer, hosted at HLRS, running at 82 percent efficiency. This is nearly a 5x increase over the record set two years ago when Fluent was scaled to 36,000 cores. “This record-setting scaling of ANSYS software on the Cray XC40 supercomputer at HLRS proves that close collaborations with customers and partners can produce exceptional results for running complex simulations,” said Fred Kohout, senior vice president and chief marketing officer at Cray.

Submissions for ISC 2017 Research Papers Due December 16

Submissions for ISC 2017 Research Paper Sessions are now being accepted through December 16, 2016. The deadline has been extended to accommodate current submissions from engineers and scientists in academia, industry and government. “The ISC research paper sessions provide first-class open forums for engineers and scientists in academia, industry and government to present and discuss issues, trends and results that will shape the future of high performance computing.”

Video: Behind the Machine at HPE

How is Hewlett Packard Enterprise reinventing the fundamental architecture on which all computers have been built for the past 60 years? In this video, HPC describes the evolution of The Machine research project – one of the largest and most complex research projects in the company’s history – and how HPE demonstrated the world’s first Memory-Driven Computing architecture.

Call for Papers: EuroPar 2017 in Santiago de Compostela

The Euro-Par 2017 conference has issued its Call for Papers. The conference takes place Aug. 28 – Sept. 1, 2017 in Santiago de Compostela, Spain. Euro-Par is the prime European conference covering all aspects of parallel and distributed processing, ranging from theory to practice, from small to the largest parallel and distributed systems and infrastructures, from […]

HIP and CAFFE Porting and Profiling with AMD’s ROCm

In this video from SC16, Ben Sander from AMD presents: HIP and CAFFE Porting and Profiling with AMD’s ROCm. “We are excited to present ROCm, the first open-source HPC/Hyperscale-class platform for GPU computing that’s also programming-language independent. We are bringing the UNIX philosophy of choice, minimalism and modular software development to GPU computing. The new ROCm foundation lets you choose or even develop tools and a language run time for your application. ROCm is built for scale; it supports multi-GPU computing in and out of server-node communication through RDMA.”

RAID Inc. Steps up with ZFS on Lustre at SC16

In this video from SC16, Brad Merchant from RAID Inc. describes the company’s new Lustre ZFS Building Block. “RAID Inc. offers a suite of building block product families that can be purchased individually or in conjunction with other RAID products to solve customer’s needs in the most demanding data-storage environments. Each product is customized to address customer’s individual requirements of performance, reliability, scalability and price. Each product is put through extensive testing and a burn-in/staging process which ensures customers will receive a solution designed to function as specified in their unique environment.”

DDN IME Burst Buffer Exceeds 1 TB/s for Japan’s Fastest Supercomputer

“Storage performance has been one of the biggest challenges in developing supercomputers. To meet the demands for storage performance, IME was introduced to the Oakforest-PACS on a massive scale, the first such introduction in the world,” said Osamu Tatebe, lead, public relations, JCAHPC / professor, Center for Computational Sciences, University of Tsukuba. “We are very pleased that we could achieve effective I/O performance exceeding 1 TB per second in writing tens of thousands of processes to the same file. With this new storage technology, we believe that we will be able to contribute to society with the further development of computational science, big data analysis and machine learning.”

Best Threads Per Core with Intel Xeon Phi

“When designing an application that contains many threads and less cores than threads, it is important to understand what is the optimal number of threads that should be assigned to a core. This value should be parameterized, in order to easily run tests to determine which is the optimum value for a given machine. One thread per core on the Intel Xeon Phi processor will give the highest performance per thread. When the number of threads per core is set at two or four, the individual thread performance may be lower, but the aggregate performance will be greater.”