IDC will hold its annual Analyst Briefing and Breakfast at SC16. Free for attendees, the event takes place 7:15 a.m. to 8:30 a.m. on Tuesday, Nov. 15 at the Hilton Salt Lake City Center. “Join IDC industry analysts as they present their expert opinions and analysis on the technical computing market and the future of high-performance computing.”
Today Emu Technology announced that it has delivered an Emu Chick Memory Server to Oak Ridge National Laboratory. “ORNL intends to study the system for streaming graph analysis applications, sparse multilinear computations, and other memory-intensive problems, as we continue to test the potential of emerging computing technologies to further our mission within the DOE,” said Jeffrey S. Vetter, Director of the Future Technologies Group at ORNL’s Computer Science and Mathematics Division.
Today Allinea Software announced that the compay will hold series of New Software Performance Briefings at SC16. The briefings will be held at the Allinea booth #1508 in Salt Lake City. This year at SC, we’re giving booth visitors the opportunity to find out more about what they don’t know about their software performance,” said […]
Today European software startup Appentra announced that its Parallware technology for guided parallelization has been selected to be part of the SC16 Emerging Technologies Showcase. “As a technology with the potential to influence computing and society as a whole, Parallware is novel LLVM-Based Software Technology for Classification of Scientific Codes to Assist in Parallelization with OpenMP and OpenACC.”
“This talk will provide empirical evidence from our Deep Speech work that application level performance (e.g. recognition accuracy) scales with data and compute, transforming some hard AI problems into problems of computational scale. It will describe the performance characteristics of Baidu’s deep learning workloads in detail, focusing on the recurrent neural networks used in Deep Speech as a case study. It will cover challenges to further improving performance, describe techniques that have allowed us to sustain 250 TFLOP/s when training a single model on a cluster of 128 GPUs, and discuss straightforward improvements that are likely to deliver even better performance.”
Martina Naughton presented this talk at the HPC Advisory Council Spain Conference. “IBM has a strong tradition of research collaboration with academia. We go beyond the boundaries of our IBM labs to work with colleagues in universities around the world to address global grand challenge problems. We also foster collaborative research related to transformation and innovation of businesses and governments, relationships through fellowships, grants, and funding for programs of shared interest.”
“The work we do involves capturing and analyzing huge environmental data sets so that the government can make informed policy decisions that protect humans and the environment,” said Ron Hines, Associate Director for Health at the EPA’s National Health and Environmental Effects Research Laboratory in Research Triangle Park, N.C. “We have collaborated with the NCDS on some of its initiatives in the past and having a seat at its leadership table will help us connect with leading data researchers, access data resources and infrastructure, and contribute to the development of future NCDS strategies.”
Today the Numerical Algorithms Group announces the latest version of its flagship software, the NAG Library, Mark 26. In this release, NAG has introduced an Optimization Modeling Suite for linear and nonlinear semidefinite programming and general nonlinear programming. It also features new routines in the important computational areas of Nearest Correlation Matrix and Quadrature.
“ISC High Performance 2017 is now open to a number of submission opportunities. Whether your interest lies in research posters, project posters, birds-of-a-feather (BoF) sessions or the PhD forum, ISC is welcoming proposals from all members of the high performance computing community. ISC High Performance is looking forward to continuing its tradition as the largest HPC conference and exhibition in Europe. It will be attended by over 3,000 academicians, industry leaders and end users from around the world. The ISC exhibition annually attracts around 150 organizations, including supercomputing, storage and network vendors, as well as universities, research centers, laboratories and international projects.”
“With up to 72 out-of-order cores, the new Intel Xeon Phi processor delivers over 3 teraFLOPS (floating-point operations per second) of double-precision peak while providing 3.5 times higher performance per watt than the previous generation. As a bootable CPU with integrated architecture, the Intel Xeon Phi processor eliminates PCIe* bottlenecks, includes on-package high-bandwidth memory, and available integrated Intel Omni-Path fabric architecture to deliver fast, low-latency performance.”