AMD wants you to build your hardware solution around their processor

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I think it’s interesting when companies embrace changes in their industry rather than ignoring it or trying to litigate it out of existence (I’m thinking of an organization, and its initials are RIAA).

AMD is doing just that by opening up it’s HyperTransport interconnect for other vendors to bolt hardware on to AMD’s product offering. Think FPGAs, co-processors, and the like. The initiative (which is not new) is called Torrenza, and you can find out more here.

AMD lists Cray, IBM, and Sun as its main OEM partners, along with a bunch of “ecosystem” partners: companies like Xilinx and QLogic.


  1. […] You add the Stream Processor in an existing system via PCI Express along with up to a gigabyte of memory. Oddly, it doesn’t connect via the Torrenza interface. The chip on the board has 48 cores, and ATM claims it can deliver 375 GFLOPS. […]

  2. […] In a move that follows what AMD has done with Torrenza (which we mentioned here), Intel announced at the last IDF it had signed up Xilinx and Altera to make products that fit into Intel sockets. …The idea is that high performance computing types, oil and gas firms and financial services companies can program the FPGAs to handle specific software loads and speed up the performance of their code. […]

  3. […] SRC Computers announced yesterday that they’ll be supporting AMD’s Torrenza initiative with their processor accelerator solutions. Recall that Torrenza is AMD’s platform for letting 3rd party vendors integrate tightly with it’s processors using HyperTransport. […]

  4. […] From HPCwire today we learn that DRC has announced the RPU110-L200, its new reconfigurable processing unit. This DRC solution integrates with the processor directly using AMD’s HyperTransport link through AMD’s Torrenza interface announced back in January. SRC announced a similar approach in June. DRC’s RPU110–L200 module plugs directly into an open processor socket in a multi-way AMD Opteron system to provide direct access to adjacent double data-rate (DDR) memory and Opteron processors at HyperTransport speed and nanosecond latency. This tight coupling between the central processing unit (CPU) and memory eliminates bandwidth and latency issues and provides a general-purpose system with supercomputer capability by running computations in hardware. […]