Cray lines up for PCI 3.0

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This week interconnect specialists Gennum Snowbush announced that Cray had selected their PCIe 3.0 technology for use in Cray’s forthcoming lineup of supers

Cray logo“After an extensive evaluation of competitive solutions, we selected Snowbush’s high speed PCIe 3.0 PHY IP because it is the best solution available in the market today. Snowbush’s reputation for high quality, reliable first-pass silicon offered our designers confidence that incorporating this IP block into our newest supercomputer design will give us a competitive edge in the market place,” said Peg Williams, Senior Vice President of Research and Development at Cray.

The specification isn’t hardened yet, but that’s expected to come toward the end of this year according to the PCI-SIG web site, with products expected in the market in 2010. PCIe 3.0 doubles the bandwidth of PCIe 2.0 to 1 GB/s, and is a more efficient protocol (version 3.0 no longer loses 20% to the overhead of the 8b/10b encoding scheme of PCIe 2.0).