Mitrionics Unveils Mitrion-C Compiler for Implicitly Parallel

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Mitrionics announced details and early performance numbers this week from a recent research project they performed internally.  The proof-of-concept compiler project was spearheaded by their chief scientist, Stefan Möhl, with a goal of providing a portable implementation of their Mitrion-C language that would run on many architectures.  The initial target architectures were FPGAs [from their various FPGA partners], GPUs and multi-core processors.

What does this mean to the HPC industry?  Optimizing code in a particular language on a particular architecture can be difficult and certainly time consuming.  Doing so for many disparate architectures that do not share common design characteristics can occupy an entire career.  This new compiler and language technology from Mitrionics is aimed at solving that problem.

The unique properties of Mitrion-C really come from its FPGA origins. FPGAs require full MIMD parallelism for each and every instruction for efficient execution. Mitrion-C was developed to capture this kind of limit-case for parallelism. To run Mitrion-C code on other less parallel platforms, you need to sequentialize the code, rather than parallelize it. The problem of automatic parallelization has turned out to be very hard. In comparison, sequentialization is quite easy.” said Stefan Möhl. “This has the potential to put an end, or at least dramatically reduce, the continuous software rewrites that are required to take advantage of new parallel computing architectures. Looking back, it should in principle work efficiently for all previous popular parallel architectures, ranging from Vector computers, SIMD machines, and multi-threaded architecture to current MPPs, clusters, GPGPUs, FPGAs, and the future’s many-core processors.”

The Mitrion-C language was originally developed to allow applications engineers the power of utilizing FPGA’s without graduate degrees in electrical engineering.  The C-like language has a interesting trait: its implicitly parallel.  This implies that data structure distribution, concurrency and threading is hidden from the user.  Applications engineers implement algorithms rather than data distribution schemes.   Very cool.

Mitrionics created a first-edition test compiler to handle their language on other architectures.  As a result, they found that scaling certain algorithms via their language/compiler stack was equally efficient on both FPGA’s and multi-core processors.  They are doing small demos using their first-rev compiler at their booth (#1006) on the SC09 show floor.

Stefan was adamant during our interview that the compiler is not production ready yet.  However, given the fantastic results they’ve achieved so far with the initial scalability testing, the engineering crews are moving full steam ahead on making it a product.  This could prove to be a very interesting technology as we move further into more exotic platforms and architectures.  For more info, read the full release here.


  1. Stefan Möhl says

    Hi John, great article! I have a comment on a small detail. The proof-of-concept compiler currently compiles untouched source to execute efficiently on FPGAs, multi-cores and Clusters, rather than GPUs. By spanning from FPGAs to Clusters in the proof-of-concept, we span a wider range of architectures than we would have done if we went to GPUs. We made this choice of targets for the proof-of-concept since we wanted as strong evidence as possible for as wide a range of architectures as possible. However, you are perfectly right in that we hope to include GPUs in the future. I am sorry if I have been confusing on that point.