Over the past 60 years HPC has changed in dramatic spurts punctuated by fairly long periods of stability. During that time we’ve been through five computing epochs in HPC, including sequential execution, sequential issue, vector, and SIMD models of computation processing. And along the way there have been excursions into dataflow, systolic, and global shared memory models.

Each of the phase changes from one model to another was precipitated by a prior change in hardware design and system architecture. Often our programming models were a consequence of the hardware designer’s art, not the result of a collaborative effort between software and hardware designers to develop the most sensible system.

Today we stand firmly in the epoch of communicating sequential processes, enabled primarily by MPI. As we look forward to achieving the goal of a sustained exaFLOPS system by the end of this decade, we asked two leading experts in the exascale community this question: are we on the cusp of a new phase change, a new revolution, in HPC, or can we extend and adapt today’s programming model to get us there?