Archives for October 2010

Xilinx Stacked Silicon Interconnect to Beat Moore's Law

This week FPGA manufacturer Xylinx announced that it can beat Moore’s Law by using stacked silicon interconnects. Using the “industry’s first stacked silicon interconnect technology,” the company is using multiple FPGA die in a single package for applications that require high-transistor and logic density. Using this unique 3D packaging will enable the company’s 7 Series […]

U of Canterbury Awards 1 Million Supercomputer Hours

Free computing is the topic of the week. We recently posted about the Rocky Mountain Supercomputing Center giving away two months of system time and Amazon’s offer of a free year on AWS. Now the University of Canterbury is offering up a million free hours of use of its BlueFern supercomputer facility. To help researchers […]

China Benchmarks World's Fastest Super: 2.5 Petaflops Powered by GPUs

Today the National Supercomputing Center in Tianjin, China announced that their new Tianhe-1A supercomputer has set a new performance record of 2.507 petaflops on the LINPACK benchmark, making it the fastest system in the world today. While these results have been submitted to TOP500.org, their semi-annual list of the world’s fastest systems will not be […]

Small Businesses: Get Two Months Free on the Big Sky Super

The Billings Gazette is not where I usually look for HPC news, but yesterday they posted this great story on the Big Sky supercomputer in Butte, one of the “better-kept secrets” in Montana. Earl Dodd, president and chief executive of the Rocky Mountain Supercomputing Center is now touring the state offering the power of HPC […]

Webinar: Voltaire Fabric Collective Accelerator Frees Up Your CPUs

Today Voltaire announced that their Fabric Collective Accelerator reduces runtime of leading commercial HPC applications by up to 30 percent when used with Platform MPI and HP servers. Voltaire FCA software accelerates MPI collective operations by using Voltaire switches and their on-board processors to offload significant parts of group communication onto the switching fabric while Voltaire […]

Still Time to Enter SC10 Student Programming Contest

There’s still time to enter the SC10 Education Program Student Programming Contest, a competitive programming November 15 in New Orleans. In this competition, students will test their ability to solve a series of Computational Science problems. Each problem has the potential to come from any of the major scientific disciplines and is almost guaranteed to […]

Interview: Nvidia Looks to the Future of GPU Computing

Mary Branscombe over at ZDNet interviews Nvidia’s CEO, Jen-Hsun Huang about how the company’s its Tesla and Fermi-based GPUs are making parallel computing mainstream. According to Huang, the challenge of realizing parallel performance is data movement: In computer graphics, the traditional APIs of the past, the ones that all failed are the ones that moved […]

Car-Parrinello Method Turns 25

The Car-Parrinello method turned 25 recently. ETH Life describes how Roberto Car and Michele Parrinello developed this groundbreaking method for computer simulation, which allowed the first quantum mechanical calculation of the molecular state – “ab initio”. In the 1980s, the dynamics of the molecules was calculated empirically, even though it was theoretically possible to calculate in […]

Community Forum on Parallel File Systems Oct. 28 at ETH Zurich

This week members of the hpc-ch community will meet at ETH Zurich for a Forum on Parallel File Systems for HPC. With the growth of the computing capacity of HPC systems, the importance of a fast access to data storage is becoming essential. The traditional solution based on NFS is not able to sustain the […]

AMD Touts Bulldozer Flex FP For Technical and Financial Applications

AMD’s John Fruehe blogs about a new feature called “Flex FP” in the company’s upcoming Bulldozer processing cores. Designed to deliver tremendous floating point capabilities for technical and financial applications, Flex FP is a single floating point unit that is shared between two integer cores in a module (so a 16-core “Interlagos” would have 8 […]