This week Fujitsu Laboratories announced the development of a receiver circuit capable of receiving communications at 56 Gbps, a world-record data rate between CPUs.
This technology makes it possible to increase bandwidth of communications between CPUs in future servers and supercomputers, even if CPU performance doubles, without increasing pin counts, and will contribute to increased performance in large-scale systems where numerous CPUs are interconnected. In addition, it complies with standards for optical-module communications, and compared to the 400-Gbps Ethernet in OIF-CEI-28G optical-module communications, the number of circuits running in parallel (number of lanes) can be halved, allowing for smaller optical modules running on less power, and higher system performance. Fujitsu Laboratories plans to apply this technology to the interfaces of CPUs and optical modules, with the goal of a practical implementation in fiscal 2016. The company is also considering applications to next-generation servers, supercomputers, and other products.
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