Parallella Tapes Out 1024-core Epiphany-V Chip

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e5Over at the Parallella Blog, Andreas Olafsson from Adapteva writes that the company has reached an important milestone on its next-generation Epiphany-V chip.

Thanks to a generous grant from DARPA, we just taped out a 16nm chip with 1024 64-bit processor cores. To give a comparison, our 4.5B transistor chip is smaller than Apple’s latest A10 chip and has 256 times as many processors. The chip offers an 80x processor density advantage over high performance chips from Intel and Nvidia.

Epiphany-V Summary:

  • 1024 64-bit RISC processors
  • 64-bit memory architecture
  • 64-bit and 32-bit IEEE floating point support
  • 64 MB of distributed on-chip SRAM
  • 1024 programmable I/O signals
  • Three 136-bit wide 2D mesh NOCs
  • 2052 separate power domains
  • Support for up to One Billion shared memory processors
  • Support for up to One Petabyte of shared memory
  • Binary compatibility with Epiphany III/IV chips
  • Custom ISA extensions for deep learning, communication, and cryptography
  • TSMC 16FF process
  • 4.56 Billion transistors, 117mm^2 silicon area
  • DARPA funded

Olafsson contends that the new chip will be suitable for large-scale supercomputing implementations leading up to exascale.

Chips will come back from TSMC in 4-5 months. We will not disclose final power and frequency numbers until silicon returns, but based on simulations we can confirm that they should be in line with the 64-core Epiphany-IV chip adjusted for process shrink, core count, and feature changes.

Download the report: Epiphany-V: A 1024 processor 64-bit RISC System-On-Chip

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