Call for Papers: Hot Interconnects

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The 25th International Symposium on High Performance Interconnects (HotI 2017) has issued its Call for Papers. The event takes place August 29-30 at the Ericsson Campus in Santa Clara, California.

Hot Interconnects is the premier international forum for researchers and developers of state-of-the-art hardware and software architectures and implementations for interconnection networks of all scales, ranging from multi-core on-chip interconnects to those within systems, clusters, data centers, and clouds. This yearly conference is attended by leaders in industry and academia. The atmosphere provides for a wealth of opportunities to interact with individuals at the forefront of this field.

Themes include cross-cutting issues spanning computer systems, networking technologies, and communication protocols for high-performance interconnection networks. This conference is directed particularly at new and exciting technology and product innovations in these areas. Contributions should focus on real experimental systems, prototypes, or leading-edge products and their performance evaluation.

In past year’s the best papers on interconnect microarchitecture have been invited to submit extended versions of their papers to a special
edition of IEEE Micro, we are pursing this once again this year. Building on last year’s successful technical program comprising keynotes, technical sessions, and panels on networking for datacenters and high-performance computing, the 2017 edition of Hot Interconnects is generously hosted by Ericsson at their campus in Santa Clara.

This year’s conference focuses on HPC and Hyperscale Data Centers Interconnects and their use in traditional and non-traditional applications, such as large scale machine learning. We hope you can join us there.

We invite paper submissions across a wide range of topics and levels, ranging from fundamentals to the latest advances in hot topic areas. Topics of interest include, but are not limited to:

  • Novel and innovative interconnect architectures
  • Multi-core processor interconnects
  • System-on-Chip Interconnects
  • Advanced chip-to-chip communication technologies
  • Optical interconnects
  • Protocol and interfaces for inter-processor communication
  • Survivability and fault-tolerance of inter-connects
  • High-speed packet processing engines and network processors
  • System and storage area network architectures and protocols
  • High-performance host-network interface architectures
  • High-bandwidth and low-latency I/O
  • Pb/s switching and routing technologies
  • Innovative architectures for supporting collective communication
  • Novel communication architectures to support cloud & grid computing
  • Centralized and distributed cloud interconnects
  • Requirements driving high-performance inter-connects
  • Traffic characterization for HPC systems and commercial data centers
  • Software-defined networking and software overlay networks
  • Software for network bring-up, configuration and performance management (OpenFlow, OpenSM)
  • Data Center Networking

Paper abstracts are due May 12, 2017.

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