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Call for Papers: HiPINEB 2018 in Vienna

The IEEE International Workshop on High-Performance Interconnection Networks in the Exascale and Big-Data Era (HiPINEB) has issued its Call for Papers. The event takes place February 25, 2018 in Vienna, Austria in conjunction with HPCA 2018 Conference.

The main goal of the fourth edition of HiPINEB is to gather and discuss in a full-day event the latest and most prominent efforts and advances, from both industry and academia, in the design and development of scalable high-performance interconnection networks, especially those oriented to meet the Exascale challenge and Big-data demands.

By the year 2023, HPC Systems are expected to break the performance barrier of the Exaflop (10^18 FLOPS) while their power consumption is kept at current levels (or increases marginally), what is known as the Exascale challenge. In addition, more storage capacity and data-access speed is demanded to HPC clusters and datacenters to manage and store huge amounts of data produced by software applications, what is known as the Big-Data challenge. Indeed, both the Exascale and Big-Data challenges are driving the technological revolution of this decade, motivating big research and development efforts from industry and academia. In this context, the interconnection network plays an essential role in the architecture of HPC systems and datacenters, as the number of processing or storage nodes to be interconnected in these systems is very likely to grow significantly to meet the higher computing and storage demands.

Besides, the capacity of the network links is expected to grow, as the roadmaps of several interconnect standards forecast. Therefore, the interconnection network should provide a high communication bandwidth and low latency, otherwise the network would become the bottleneck of the entire system. In that regard, many design aspects are considered when it comes to improving the interconnection network performance, such as topology, routing algorithm, power consumption, reliability and fault tolerance, congestion control, programming models, control software, etc.

All researchers and professionals, from both industry and academia, working in the area of interconnection networks for scalable HPC systems and Datacenters are encouraged to submit an original paper to the workshop and to attend this event.

The list of topics covered by this workshop includes, but is not limited to, the following:

  • Interconnect architectures and network technologies for high-speed, low-latency interconnects
  • Scalable network topologies, suitable for interconnecting a huge number of nodes
  • Power saving policies in the interconnect devices and network infrastructure, both at software and hardware level
  • Good practices in the configuration of the network control software
  • Network communication protocols: MPI, RDMA, MapReduce, etc.
  • APIs and support for programming models
  • Routing algorithms
  • Quality of Service (QoS)
  • Reliability and Fault tolerance
  • Load balancing and traffic scheduling
  • Network Virtualization
  • Congestion Management
  • Applications and Traffic characterization
  • Modeling and simulation tools
  • Performance Evaluation
  • Interfacing accelerators through the interconnect (GPUs, Xeon Phi, etc)
  • Network infrastructure in distributed storage, distributed databases and Big-Data

Submissions are due January 8, 2018.

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