The eight annual International Workshop on Accelerators and Hybrid Exascale Systems (AsHES) has issued its Call for Papers. Held in conjunction with the 32nd IEEE International Parallel and Distributed Processing Symposium, the AsHES Workshop takes place May 23 in Vancouver, Canada.
This workshop focuses on understanding the implications of accelerators and heterogeneous designs on the hardware systems, porting applications, performing compiler optimizations, and developing programming environments for current and emerging systems. It seeks to ground accelerator research through studies of application kernels or whole applications on such systems, as well as tools and libraries that improve the performance and productivity of applications on these systems.
Suggested Topics include:
- Strategies for programming heterogeneous systems using high-level models such as OpenMP, OpenACC, low-level models such as OpenCL, CUDA
- Methods and tools to tackle challenges in scientific computing at extreme scale
- Strategies for application behavior characterization and performance optimization for accelerators
- Techniques for optimizing kernels for execution on GPGPU, Intel Xeon Phi, and future heterogeneous platforms
- Models of application performance on heterogeneous and accelerated HPC systems
- Compiler Optimizations and tuning heterogeneous systems including parallelization, loop transformation, locality optimizations, Vectorization
- Implications of workload characterization in heterogeneous and accelerated architecture design;
- Benchmarking and performance evaluation for accelerators
- Tools and techniques to address both performance and correctness to assist application development for accelerators and heterogeneous processors
- System software techniques to abstract application domain-specific functionalities for accelerators
The goal of this workshop is to bring together researchers and practitioners who are involved in application studies for accelerators and other heterogeneous systems, to learn the opportunities and challenges in future design trends for HPC applications and systems.
Submissions are due January 31, 2018.
