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Realizing Exabyte-scale PM Centric Architectures and Memory Fabrics

Zvonimir Bandic is Senior Director, Research and Development Engineering at Western Digital Corporation.

In this video from the SNIA Persistent Memory Summit, Zvonimir Bandic from Western Digital presents: Realizing the Next Generation of Exabyte-scale PM Centric Architectures and Memory Fabrics.

In the last five years, the increasing volume, velocity and variety of data generated and consumed by Big Data and Fast Data applications has driven an aggressive pursuit for the next generation of emerging non-volatile memories, particularly in the area of persistent memory. At component level, this memory must be byte-addressable and non-volatile, deliver latency comparable to DRAM, but have density and cost that falls somewhere between DRAM and NAND flash.

Much has been debated about would it take to scale a system to exabyte main memory with the right levels of latencies to address the world’s growing and diverse data needs. This presentation will explore legacy distributed system architectures based on traditional CPU and peripheral attachment of persistent memory, scaled out through the use of RDMA networking. It will discuss the present boundaries of memory and compute technologies, and the many considerations for developing persistent memory, including performance, power, latency requirements and cost merits of parallel and serial attachment points for memories, and show the experimentally measured latency of RDMA access to persistent memory devices.

This presentation will also consider a theoretical question of what would it take to scale a system to exabyte main memory from the perspective of networking fabric required to access such large amounts of main memory at useful latencies. It will explore the “exabyte challenge” from the hardware architecture perspective and, given the present boundaries of memory and compute technologies, quantitatively evaluate latency requirements for memory and memory fabric switch devices. In addition, it will address the ramifications of the large memory footprint of persistent memory for emerging data-intensive workloads, such as high performance data analytics, autonomous vehicles, social networking value extraction, and many traditional memory bound workloads. Finally, it will outline a vision for a prototyping platform for accelerating innovation in networking protocols that will enable experimental evaluation of novel memory fabrics at scale.

Zvonimir Z. Bandić is the Research Staff Member and Senior Director of Next Generation Platform Technologies at Western Digital Corporation. He is currently focusing on emerging Non-Volatile Memories (PCM, ReRAM, MRAM) applications for data center, distributed computing, including RISC-V based CPU technologies, in-memory compute, RDMA networking, and machine learning hardware acceleration. He received his BS in electrical engineering in from the University of Belgrade, Yugoslavia, and his MS and PhD in applied physics from Caltech, Pasadena, in the field of novel electronic devices based on wide bandgap semiconductors. He has been awarded over 50 patents in the fields of solid state electronics, solid state disk controller technology, security architecture and storage systems and has published over 50 peer-reviewed papers.

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