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Video: Calligo Technologies Demonstrates Posit Computing Implementation

Anantha Kinnal from Calligo Technologies

In this video from the CoNGA Conference for Next Generation ArithmeticAnantha Kinnal from Calligo Technologies demonstrates the company’s Posit computing technology.

“CalligoTech, based in Bangalore – India, built and demonstrated World’s First Posit-enabled System at the CoNGA track at Supercomputing Asia’18, Singapore. Our primary objective was to build a System capable of performing basic arithmetic operations using Posit Number System and capable of running existing C programs.”

The Posit number system is a flexible number system with variable no of bits (n) and exponent size (es). Any specific configuration is represented as <n,es> format. We selected to implement a Posit Numeric Unit (PNU) with <32,2> configuration targeting HPC applications and to be able to compare advantages of Posit with Single Precision Floats for dynamic range and with Double Precision Floats for accuracy.

We chose to implement the PNU design using FPGAs on a Single Board Computer with Intel Arria10 SOC-FPGA, running Linux. The SOC-FPGA comes with dual-core ARM Cortex-A9 MPCore Processor with native FPU and different capacity FPGAs. FPGAs offer field-upgrade and capability to change the design in seconds just by reprogramming using different bit-stream. This flexibility is absolutely necessary for an evolving standard, to quickly fix bugs and to add new functionality. We use a host computer connecting to the SBC over Ethernet. It runs a docker environment containing cross-compiler, general and special libraries.”

Top-level interface for the PNU is Input Operands and Opcode, and Output Result. There are some control-status registers and hooks for interrupts & exceptions. The advantage of this simple top-level interface is that it can be integrated with any CPU, by designing the interface glue-logic.

In this first version of the design, we implement basic arithmetic operations – Addition, Subtraction, Multiplication, Divide, Sqrt, Quire, integer ←→ Posit conversions is being added. Logic for supporting Transcendental functions is planned.

Our current design comes in two formats – first one is a PNU that takes 32-bit Posit operands in <32,2> format, 5-bit opcode and generates result in Posit <32,2> format. This is used in a C-based test-bench environment to exhaustively validate the functionality of the PNU for millions of vectors.

The second format of the design is a wrapper around the PNU. Input operands in this case is 32/64-bit Floats, converted to Posit <32,2> format and fed to the PNU. Posit result generated is converted back to 32/64-bit Float format. Advantage of this form of the design is that we can run any existing C-program, but compute using Posit Numeric Unit instead of FPU. One has to compile the C program with –mfloat-abi = soft option and link with a special library that drives the input operands in 32/64-bit Float format.

CalligoTech delivered the first system to Institute of High Performance Computing, Singapore – an A*STAR Research Entity and is currently selling this version of the Product worldwide. Those interested in more information / purchasing this Product may please write to sales@calligotech.com.

To demonstrate the real power of Posit Number System and its advantages, CalligoTech is working on tape-out of PNU tightly integrated with CPUs.

Anantha Kinnal is the Co-founder & Director at Calligo Technologies Pvt Ltd, Bangalore, India – a Company focused on products / services for HPC, Big-Data and AI markets. He is responsible for development of products for High Performance Computing market such as PNU and FPGA-based Accelerators for Scientific / Business computing.

He comes with 30+ years of experience in CPU design companies, largely X86, as – Director of Engineering at AMD-India, Senior Design Engineering Manager at Intel-India on multiple Xeon CPU designs. He worked at NexGen, California based start-up acquired by AMD, on Nx-587(FPU) & Nx-686(CPU) and AMD-K6 & K8 CPU programs. While at AMD, he started the CPU Design Centre at AMD-Singapore and led the X86-64 design team for a year. Prior to this, he worked at Bull S A (France) as Chief Architect and Project Manager responsible for IO Sub-system connectivity to Mainframe CPU Sub-system. In early part of his career, he worked on Reverse Engineering of PDP-11 CPU using Micro-programmable hardware, at PSI Data Systems, Bangalore – India.

In this video from the HPC Advisory Council Australia ConferenceJohn Gustafson from the National University of Singapore presents: Beating Floating Point at its own game – Posit Arithmetic.

“Dr. Gustafson has recently finished writing a book, The End of Error: Unum Computing, that presents a new approach to computer arithmetic: the unum. The universal number, or unum format, encompasses all IEEE floating-point formats as well as fixed-point and exact integer arithmetic. This approach obtains more accurate answers than floating-point arithmetic yet uses fewer bits in many cases, saving memory, bandwidth, energy, and power.”

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