Today Micron Technology announced that it has begun sampling DDR5 registered DIMMs, based on its industry-leading 1znm process technology, with key industry partners. DDR5, the most technologically advanced DRAM to date, will enable the next generation of server workloads by delivering more than an 85% increase in memory performance. DDR5 doubles memory density while improving reliability at a time when data center system architects are seeking to supply rapidly growing processor core counts with increased memory bandwidth and capacity.
Data center workloads will be increasingly challenged to extract value from the explosive growth of data across all aspects of our business and personal lives,” said Tom Eby, senior vice president and general manager of the Compute & Networking Business Unit at Micron. “The key to enabling these workloads is higher quality memory that is faster and denser. Micron’s sampling of DDR5 RDIMMs represents a milestone for server platforms as it brings the industry one step closer to harnessing the scaling capability of next generation memory.”
Advanced workloads, fueled by ever-growing datasets and compute-intensive applications, have driven an explosion of processor core counts in the data center which will be bandwidth-starved by current DRAM technology. DDR5 delivers higher bandwidths and bigger densities, and it enables the increased reliability, availability and scaling that modern data centers require.
The DDR5 bandwidth entry point delivers more than 1.85-times increase in performance compared to standard DDR4. DDR5 also features superior data-transfer performance, making significantly more efficient use of CPU clock cycles and system resources.
With a robust list of new and enhanced features targeted at improving performance and reliability — like doubled burst lengths, bank groups and banks alongside improved refresh granularity — DDR5 is not just a generational improvement over DDR4. It’s a fundamental redefinition of SDRAM performance, pushing the limits of high-speed signaling and directly addressing the memory bandwidth challenge.
