Reinventing HPC Architectures with In-Package Optical I/O

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Even with the first exascale systems coming soon, HPC centers are searching for the technologies that will provide post-exascale levels of processing, bandwidth, and memory. Given space constraints and the limitations of current materials, chips are running up against the laws of physics, making gains from clever engineering harder to come by. Without some significant breakthroughs, it will be increasingly difficult to improve the computing power available per dollar.

Industry players are exploring the problem from many angles, including ways to increase overall performance and efficiency at the system level.

Faster Interconnects for Revolutionary System Innovation

In HPC centers and labs, as models continue to grow and scientific workloads become more demanding, faster interconnects will be critical to improving and innovating systems in ways not currently possible. For example, by enabling system architects to decouple memory from processors and accelerators, disaggregated – or high-throughput data-centric – architectures can be built.

Although the industry has long recognized the potential of optical I/O as a solution for many HPC challenges, it is only in recent years that economic in-package optical solutions have become available. Matt Leininger, Senior Principal HPC Strategist in the Advanced Technology Office at Lawrence Livermore National Laboratory (LLNL), says our awareness of optical technology as a potential game changer goes back to the turn of the century:

“Twenty years ago, the Internet boom promised to develop optical I/O technologies that would solve some of our biggest challenges. However, incremental improvements in traditional technologies won out. Today, we know what technologies are necessary for the first and second generation of Exascale platforms in the 2022 to 2023 timeframe, but after that a crossover to optical I/O based solutions will be needed.”

Optical I/O to Drive Post-Exascale Progress

At last, optical I/O has emerged as the best solution to drive the next phase of Moore’s Law-like advances in post-exascale systems performance. In part this is because there have not been game-changing breakthroughs in the materials used in traditional interconnects. The result: I/O progress has remained relatively flat over the years as the byte per FLOP (B/F) ratio has steadily decreased, limiting the ability of CPUs and HPC systems, bogged down by insufficient bandwidth, to run at their full  potential.

Ayar Labs has developed a way to use standard silicon fabrication techniques to replace traditional electrical-based I/O with high speed, high density, low power optical-based interconnect “chiplets” and disaggregated multi-wavelength lasers. The company’s technology will support significantly faster interconnects and new system architectures that will enable HPC centers to continue to push boundaries for HPC and AI.

A Dramatic Increase in Bandwidth while Reducing Latency and Power

Ayar Labs optical I/O chiplets provide universal I/O that enables truly disaggregated and distributed architectures in support of more flexible systems in which all the components are “first-class citizens,” distributing data to all systems components –processing and memory – when and where it is needed. The company’s TeraPHY™ in-package optical I/O technology provides 100 – 1,000x the bandwidth available through electrical options, eliminating bandwidth issues. Compared to ethernet solutions that rely on switches and forward error correction (FEC), FEC-less links directly from the host SoC in TeraPHY chiplets reduce off-package latency by a factor of 10 (end-to-end connections of ~10 ns plus time of flight versus ~100 ns plus time of flight for ethernet). Beyond the bandwidth and low latency gains, Ayar Labs optical technology also significantly reduces energy consumption, requiring only about a 10th of the power required to move a bit of data electrically.

Another key benefit of TeraPHY chiplets: they can effectively provide off-package communication at the cost of in-package communication. HPC centers will be able to build flexible systems that use optical I/O directly from any SoC package to connect heterogeneous technologies and more easily support a wide mix of applications with different scaling trends. TeraPHY chiplets have high-bandwidth density that enables high fanout from the package in support of glueless interconnects, as well as shallow high-radix switched topologies. Enabling every element in the system to communicate with low latency makes it easier to create custom “supernodes” for supporting specific workloads.

Learn more about the in-package optical I/O for HPC in our white paper: “Paradigm Change: Reinventing HPC Architectures with In-Package Optical I/O”

Check out this video for the latest Ayar Labs update and technology demo

For more information about Ayar Labs and their in-package optical I/O technology, visit