SiPearl, the company designing the Rhea microprocessor for the European exascale supercomputer, announced it has passed a milestone before the chip’s scheduled 2022 launch. The company said it is moving into an “accelerated simulation phase” on the Veloce Strato hardware emulator from Siemens Digital Industries Software.
SiPeal said the hardware emulation platform provides its chips designers with a high-speed verification environment letting them accelerate pre-silicon, pre-production functional verification in a virtual environment.
The Veloce Strato platform has capacity scaling up to 15B Gate. It is designed to deliver fast compilation and comprehensive design visibility for verification of advanced chip designs.
“Thanks to our collaboration with Siemens, as we prepare for Rhea’s arrival on the market, we are able to benefit from a powerful and flexible emulation infrastructure, combined with the team’s expertise, which enables us to accelerate its simulation with uncompromised visibility and debug. This technological choice also sets out our strong commitment to our future clients with a view to supporting their own performance levels,” said Philippe Notton, CEO and founder of SiPearl, the Franco-German company supporting the European Processor Initiative.
