GUC Tapes Out AI/HPC/Networking Platform on TSMC CoWoS Technology with 7.2 Gbps HBM3 Controller and PHY, GLink-2.5D and 112G-LR SerDes IPs

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Hsinchu, Taiwan – June 8, 2021 – Global Unichip Corp. (GUC), the Advanced ASIC Leader, announced today that it has successfully taped out AI/HPC/Networking CoWoS Platform with 7.2 Gbps HBM3 Controller and PHY, GLink-2.5D and third-party 112G-LR SerDes IPs. The main die of the platform contains the world’s first HBM3 Controller and PHY IP with a record-high 7.2 Gbps performance.

The platform meets strict signal and power integrity (SI and PI) requirements of 112G-LR SerDes routed through TSMC CoWoS technologies. GUC’s GLink-2.5D interface enables high bandwidth, low latency, low power interconnection of several dies on the CoWoS platform. The success of the tape out breaks the limits of memory bandwidth and unleashes new potential for scalable Artificial Intelligence (AI), High Performance Computing (HPC), and Networking multi-die solutions.

The platform represents real AI/HPC/Networking applications usage cases which require the high flexibility of SoC floorplans and HBM3 PHY/Controller arrangements on the main die vs. HBM3 memory on interposers. GUC’s patent-pending solution allows HBM3 bus routing between PHY and memory at any angle while keeping the same signal width and space as in traditional straight HBM bus routing. It allows shorter routing, better signal integrity, higher speed and lower power consumption than traditional zig-zag HBM bus routing. Our products can support up to 10 HBM3 memories connected to two SoC dies by using splitting PHY technology. GUC’s patent-pending solution enables the splitting of the central HBM3 memory bus to PHYs, located on two SoC dies to allow full HBM3 utilization in 2:6 or 2:10 SoC:HBM3 memory use cases.

GUC’s design for CoWoS and interposer supports 112G-LR SerDes signaling by adopting in-house interposer design flow and the latest TSMC CoWoS technology. To represent typical AI/HPC/Networking chip conditions, multiple instances of HBM3, 112G-LR SerDes and GLink-2.5D IPs were integrated into this big die CoWoS platform with high power consumption. GUC implemented a high coverage DFT solution for both wafer-level and final production tests. The DFT solution takes advantage of HBM3 and GLink-2.5D lane redundancy and repair to maximize CoWoS yield.

“We are proud to be the world’s first company to tape out a full-scale 7.2 Gbps HBM3 controller and PHY IP. GUC has again demonstrated industry leadership in offering a total solution for advanced packaging technology.”, said Dr. Ken Chen, president of GUC. “We have complemented our HBM2E PHY/Controller, GLink-2.5D and GLink-3D IP portfolio with HBM3. Together with CoWoS, InFO_oS, 3DIC design expertise, package design, electrical and thermal simulations, DFT and production testing, we provide cutting edge solutions to our customers and assist them to achieve even greater success in their products and businesses.”

“We integrated multiple instances of HBM3, 112G-LR SerDes and GLink-2.5D IPs and much highly complex toggling logic in 280 mm2, 400W die and assembled multiple dies and HBM3 memories on a CoWoS platform. It validates our IPs at large scale AI/HPC/Networking chip conditions and brings the high confidence of our IPs robust operation to high scale products.” said Igor Elkanovich, CTO of GUC. “We used our multi-lane 112Gbps package design expertise together with silicon-correlated high-speed interposer design flow to validate 112Gbps over the latest CoWoS solution.”

Key features of the GUC’s AI/HPC/Networking CoWoS Platform:

  • World 1st full functional HBM3 Controller and PHY at 7.2 Gbps
  • CoWoS interposer and package meet tight 112G-LR SerDes requirements
  • GLink-2.5D interface connecting multiple dies over CoWoS
  • 280 mm2 single die with 400W configurable power consumption and multiple dies assembly on CoWoS together with HBM3 memories
  • GUC’s patent-pending interposer routing to support any angle zig-zag routing, and split HBM3 PHY into two SoCs usage
  • Full DFT solution for both wafer test and final test of assembled dies including HBM3 and GLink-2.5D lane redundancy and repair