“Achieving error rates well below one percent is a big step toward the broader commercialization of quantum computing,” said Chad Rigetti, founder and CEO of Rigetti. “We believe it opens up a new regime for algorithm R&D, which includes practical application development, quantum advantage benchmarking, and empirical tests of quantum error correction.”

Today’s quantum computers are prone to errors, which limit the size and complexity of problems that can be encoded and processed on them. Reducing these errors is the focus of many efforts across the industry and is widely believed to be one of the key characteristics for commercial quantum computers, along with scale, speed, reprogrammability, and co-processing.

Rigetti‘s next-generation chip architecture builds on its previous processors, including 3D signal delivery and superconducting caps and vias, which are designed to reduce crosstalk among qubits on the chip. It also incorporates recent advances in qubit design and gate operations, which the company has published previously. Internal measurements on a 9-qubit test device demonstrate two-qubit gate fidelities as high as 99.5% and a median fidelity of 99.2%.

Rigetti said it will continue to scale test devices to higher qubit counts. Once scaled, the company intends to incorporate the new design into its proprietary modular chip architecture, with the goal of bringing together advancements in scalability, speed, and fidelity. Rigetti introduced its multi-chip processor technology last year, and recently announced the commercial availability of its 80Q Aspen-M system, the first processor generation based on this scalable architecture.