This comes on the heels of other news from Avery Design Systems this week including support for CXL 3.0 and that its NVMe, PCIe, and AXI VIP have been adopted by TenaFe for new solid state storage controllers.
A key application for utilizing Ethernet VIP is NVMe-over-TCP which applies TCP application interfaces in pure software-only host driver or optimized hardware offload to implement disaggregated, composable block storage systems across a standard IP and Ethernet network. Alternatively, in large, distributed compute server architectures, designers can incorporate NVMe-MI in-band usage models over IP control path networks for centralized discover and control
“Leveraging the bandwidth and performance of Ethernet has become increasingly important in a range of data transfer intensive applications and time-to-market is a major concern for product developers. Performing full hardware/software, system-level verification of DPUs, SmartNICs, switches, and routers can be accelerated by weeks to months using virtual network co-simulation. With this solution, any host OS or guest OS (VM) user space program or Linux network utility can communicate with SoC RTL/FW via Avery’s SystemVerilog MAC/PHY virtual NIC VIP,” said Chris Browy, vice president of sales and marketing at Avery.
Examples of real programs or utilities supported include:
· SSH
· Linux kernel SW-based IPsec/MACsec
· TCP/IP client-server programs
· NVMe-oF SDKs particularly NVMe/TCP but including NVMe/RoCE, NVMe/iWARP
· Custom OS drivers, SDKs, and user space programs
The virtual network device can be viewed as a simple Ethernet device, which instead of receiving packets from a physical media (Ethernet NIC), receives them from the Ethernet MAC/PHY RX VIP which passes them up to the OS network stack. The Ethernet MAC/PHY VIP is connected to the SoC design’s interfaces that are both part of the SystemVerilog simulation testbench.
Conversely, instead of the OS network stack sending packets via physical media they get sent through the Ethernet MAC/PHY VIP towards the SoC design’s ethernet RX interfaces.
