Intel Alters HPC-AI Roadmap: ‘Rialto Bridge’ GPU Discontinued

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After business hours on Friday, Intel released information on a “streamlined and simplified” data center GPU roadmap with direct impact on HPC and AI. The new plan calls for the discontinuation of the “Rialto Bridge” GPU, which was to have succeeded the Ponte Vecchio chip that itself was delayed several years before shipments began last year.

In its place, Intel said it will move to a two-year cadence for data center GPUs, starting in 2025 with “Falcon Shores,” part of the Max Series GPUs officially launched two months ago.

“We have simplified our roadmap with the goal of doing fewer things better and are rapidly rolling out products to our customers,” said Intel’s Jeff McVeigh, corporate VP and interim GM, Accelerated Computing Systems and Graphics in a Friday blog post.

The announcement continues an unsettled Intel roadmap going back about five years within its advanced data center chip portfolio as the company works to keep up with rising competition from chip companies NVIDIA and AMD. Delays in the development of Ponte Vecchio and in the Sapphire Rapids 4th Gen Xeon Scalable CPU in turn stalled installation of the Aurora exascale-class supercomputer at Argonne National Laboratory.

While Argonne officials have been upbeat about the ongoing Aurora install, the updated timeline calls for the system to be accessible to early researchers by the third quarter of 2023. The Department of Energy’s initial exascale plan had tabbed Aurora, with Intel as prime contractor, to become the first exaFLOP-class system in 2021. Instead, that milestone was achieved by the HPE-built, AMD-powered Frontier supercomputer at Oak Ridge National Laboratory.

Aurora exascale supercomputer

Stating that Rialto Bridge “was intended to provide incremental improvements over our current architecture,” McVeigh said, “With a goal of maximizing return on investment for customers, we will move to a two-year cadence for data center GPUs. This matches customer expectations on new product introductions and allows time to develop their ecosystems.”

He said Falcon Shores will have a flexible chiplet-based architecture suited to AI, HPC and the convergence of the two markets. “This foundational architecture will have the flexibility to integrate new IP (including CPU cores and other chiplets) from Intel and customers over time, manufactured using our IDM 2.0 model.”