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Call for Workshops: HiPEAC 2020 in Bologna

The HiPEAC 2020 conference has issued its Call for Workshops. The event takes place January 20-22, 2020 in Bologna, Italy. “The HiPEAC conference is the meeting place for computing systems researchers in Europe. Put your research on the map with a paper presentation and get your paper published in the open access journal ACM TACO: Transactions on Architecture and Code Optimization.”

Epic HPC Road Trip Continues to NCAR

In this special guest feature, Dan Olds from OrionX continues his Epic HPC Road Trip series with a stop at NCAR in Boulder. “Their ability to increase model precision/resolution and to increase throughput at the same time is becoming more difficult over time due to core speed slowing down as more cores are added. In other words, new chips aren’t providing the same increase in performance as we’ve become accustomed to over the years.”

New Paper: Nanophotonic Neural Networks coming Closer to Reality

Over at the Intel AI blog, Casimir Wierzynski writes that Optical Neural Networks have exciting potential for power-efficiency in AI computation. “At last week’s CLEO conference, we and our collaborators at UC Berkeley presented new findings around ONNs, including a proposal for how that original work could be extended in the face of real-world manufacturing constraints to bring nanophotonic neural network circuits one step closer to a practical reality.”

New Dell EMC AI Experience Zones Launch in Asia

Today Dell EMC launched a set of new Dell EMC AI Experience Zones in Bangalore, Seoul, Singapore, Sydney, and Tokyo. “The Dell EMC AI Experience Zones provide a unique space where customers and our partners can explore, test out, and learn about the different physical and virtual components that make up an AI ecosystem. This initiative is the focal point of our commitment to fostering knowledge sharing between CIOs, our ready team of technology experts, and industry partners to accelerate AI adoption and innovation for the region.”

Video: Perlmutter – A 2020 Pre-Exascale GPU-accelerated System for NERSC

Nick Wright from Lawrence Berkeley Lab gave this talk at the GPU Technology Conference. “We’ll present an overview of the upcoming NERSC9 system architecture, throughput model, and application readiness efforts. Perlmutter, a Cray system based on the Shasta architecture, will be a heterogeneous system comprising both CPU-only and GPU-accelerated nodes, with a performance of more than 3 times Cori, NERSC’s current platform.”

GCS Sponsors University Teams for ISC19 Student Cluster Competition

The Gauss Centre for Supercomputing is sponsoring the two German student teams for the Student Cluster Competition at ISC 2019 in Frankfurt. The teams, representing the University of Hamburg and Heidelberg University, are among the 14 student teams from Asia, North America, Africa, and Europe that will go head to head on the exhibition show floor.

Forum Teratec to Spotlight HPC, AI, and Digital Transformation in Europe

Registration is now open for the Forum Teratec in France. The event takes place June 11-12 in Palaiseau. “The Forum Teratec is the premier international meeting for all players in HPC, Simulation, Big Data and Machine Learning (AI). It is a unique place of exchange and sharing for professionals in the sector. Come and discover the innovations that will revolutionize practices in industry and in many other fields of activity.”

GPU Hackathon gears up for Future Perlmutter Supercomputer

NERSC recently hosted its first user hackathon to begin preparing key codes for the next-generation architecture of the Perlmutter system. Over four days, experts from NERSC, Cray, and NVIDIA worked with application code teams to help them gain new understanding of the performance characteristics of their applications and optimize their codes for the GPU processors in Perlmutter. “By starting this process early, the code teams will be well prepared for running on GPUs when NERSC deploys the Perlmutter system in 2020.”

Catalyst UK Program Fosters Arm-based HPC Systems

“Clearly Arm will fit in as part of a broader HPC ecosystem, as we move towards systems that involve multiple chip architectures. In terms of scientific research, it may mean we run one stage of a simulation workflow on an Arm processor, while another stage is best carried out on another processor. By building a common fabric with multiple architectures on it, we can allow users to use the most appropriate hardware for each stage of their particular research problem.”

The Pending Age of Exascale

In this special guest feature from Scientific Computing World, Robert Roe looks at advances in exascale computing and the impact of AI on HPC development. “There is a lot of co-development, AI and HPC are not mutually exclusive. They both need high-speed interconnects and very fast storage. It just so happens that AI functions better on GPUs. HPC has GPUs in abundance, so they mix very well.”