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Codeplay Releases First Fully-Conformant SYCL 1.2.1 Solution for C++

SYCL is an open standard developed by the Khronos Group that enables developers to write code for heterogeneous systems using standard C++. Developers are looking at how they can accelerate their applications without having to write optimized processor specific code. SYCL is the industry standard for C++ acceleration, giving developers a platform to write high-performance code in standard C++, unlocking the performance of accelerators and specialized processors from companies such as AMD, Intel, Renesas, and Arm.

Job of the Week: HPC Software Developer at the Hierarchical Data Format (HDF) Group

The Hierarchical Data Format (HDF) Group in Champaign, Illinois is seeking an HPC Software Developer our Job of the Week. “The HPC Software Developer will develop software for the Hierarchical Data Format v5 (HDF5) library and tool suite. Responsibilities will include enhancing the HDF5 library with additional features such as: sophisticated caching techniques, asynchronous file I/O, self-tuning storage optimizations, advanced multi-thread/multi-process/multi-client file access techniques, cluster and parallel file system interaction optimizations to deliver the highest performance possible to users of HDF5. Parallel and distributed I/O in high performance computing environments using MPI and MPI-IO will be the primary focus of this position. Interest and experience with project management is preferred. Some travel to client sites and to workshops and conferences may be required.”

Video: Intro to OpenMP

In this video, Markus Eisenbach and Dmitry Liakh from ORNL present: Intro to OpenMP, Part 1. “This video was recorded as part of the “Introduction to HPC” workshop that took place at ORNL from June 26-28. This is video 1 of 2, which gives a brief overview of parallel computing with OpenMP.”

Porting HPC Codes with Directives and OpenACC

In this video from ISC 2018, Michael Wolfe from OpenACC.org describes how scientists can port their code to accelerated computing. “OpenACC is a user-driven directive-based performance-portable parallel programming model designed for scientists and engineers interested in porting their codes to a wide-variety of heterogeneous HPC hardware platforms and architectures with significantly less programming effort than required with a low-level model.”

OpenACC Helps Scientists Port their code at the Center for Application Readiness (CARR)

In this video, Jack Wells from the Oak Ridge Leadership Computing Facility and Duncan Poole from NVIDIA describe how OpenACC enabled them to port their codes to the new Summit supercomputer. “In preparation for next-generation supercomputer Summit, the Oak Ridge Leadership Computing Facility (OLCF) selected 13 partnership projects into its Center for Accelerated Application Readiness (CAAR) program. A collaborative effort of application development teams and staff from the OLCF Scientific Computing group, CAAR is focused on redesigning, porting, and optimizing application codes for Summit’s hybrid CPU–GPU architecture.”

Accelerate Your Applications: CesgaHack returns to Spain in September

The Galicia Supercomputing Center (CESGA) and Appentra Solutions will host the third edition of the hackathon at the Galicia Supercomputing Center, in Santiago de Compostela, from 24th to 28th September 2018. “CESGAHack 3 will help scientists and application developers to answer more scientific question by speeding up their application runtime and also reducing how long they spend coding the improved runtime. Participants get access to the Finis Terrae II supercomputer at CESGA and a team of mentors that are experts in the optimization, parallelization and execution of HPC applications.”

Video: Speed Your Code with Intel Parallel Studio XE

“Modern processors perform their best with parallel code that’s both vectorized and threaded, which can run more than 100 times faster more than serial code. So how can you accomplish this more easily through parallel programming? Enter Parallel Studio XE, a suite of tools that simplifies and speeds the design, building, tuning, and scaling of applications with the latest code modernization methods.”

Maximizing Performance of HiFUN* CFD Solver on Intel® Xeon® Scalable Processor With Intel MPI Library

The HiFUN CFD solver shows that the latest-generation Intel Xeon Scalable processor enhances single-node performance due to the availability of large cache, higher core density per CPU, higher memory speed, and larger memory bandwidth. The higher core density improves intra-node parallel performance that permits users to build more compact clusters for a given number of processor cores. This permits the HiFUN solver to exploit better cache utilization that contributes to super-linear performance gained through the combination of a high-performance interconnect between nodes and the highly-optimized Intel® MPI Library.

Inside the Volta GPU Architecture and CUDA 9

“This presentation will give an overview about the new NVIDIA Volta GPU architecture and the latest CUDA 9 release. The NVIDIA Volta architecture powers the worlds most advanced data center GPU for AI, HPC, and Graphics. Volta features a new Streaming Multiprocessor (SM) architecture and includes enhanced features like NVLINK2 and the Multi-Process Service (MPS) that delivers major improvements in performance, energy efficiency, and ease of programmability. You”ll learn about new programming model enhancements and performance improvements in the latest CUDA9 release.”

Call For Presentations: MVAPICH User Group Meeting (MUG 2018)

The MVAPICH User Group Meeting (MUG 2018) has issued its Call For Presentations. The event will take place from August 6-8 in Columbus, Ohio. “MUG aims to bring together MVAPICH2 users, researchers, developers, and system administrators to share their experience and knowledge and learn from each other. The event includes Keynote Talks, Invited Tutorials, Invited Talks, Contributed Presentations, Open MIC session, hands-on sessions  MVAPICH developers, etc.”