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Job of the Week: Software Engineer at NCAR

NCAR in Boulder is seeking a Software Engineer in our Job of the Week. “This position focuses primarily on the development of tools to meet the needs for the NCAR/IT community, and the design, writing, implementation, and support for systems monitoring tools necessary for the management of the computer infrastructure. Support will also be provided to the research community for the development of web-based analysis tools and general web programming.”

OpenACC Brings Directives to Accelerated Computing at ISC 2017

In this video from ISC 2017, Sunita Chandrasekaran and Michael Wolfe describe how OpenACC makes GPU-accelerated computing more accessible to scientists and engineers. “OpenACC is a user-driven directive-based performance-portable parallel programming model designed for scientists and engineers interested in porting their codes to a wide-variety of heterogeneous HPC hardware platforms and architectures with significantly less programming effort than required with a low-level model.”

Agenda Posted: August MVAPICH User Group Meeting in Ohio

The MVAPICH User Group Meeting (MUG) has posted its meeting agenda. The event takes place August 14-16, 2017 in Columbus, Ohio. “As the annual gathering of MVAPICH2 users, researchers, developers, and system administrators, the MUG event includes Keynote Talks, Invited Tutorials, Invited Talks, Contributed Presentations, Open MIC session, and hands-on sessions.”

Video: Towards Quantum High Performance Computing

“Following an introduction to the exceptional computational power of quantum computers using analogies with classical high performance computing systems, I will discuss real-world application problems that can be tackled on medium scale quantum computers but not on post exa-scale classical computers. I will motivate hardware software co-design of quantum accelerators to classical supercomputers and the need for educating a new generation of quantum software engineers with knowledge both in quantum computing and in high performance computing.”

Intel Launches Movidius Neural Compute Stick

Today, Intel launched the Movidius Neural Compute Stick, the world’s first USB-based deep learning inference kit and self-contained artificial intelligence accelerator that delivers dedicated deep neural network processing capabilities to a wide range of host devices at the edge. Designed for product developers, researchers and makers, the Movidius Neural Compute Stick aims to reduce barriers to developing, tuning and deploying AI applications by delivering dedicated high-performance deep-neural network processing in a small form factor.

Interview: The Computational Challenges of Fusion Energy

In this video from PASC17, Yasuhiro Idomura from the Japan Atomic Energy Agency and Laurent Villard from EPFL discuss the computational challenges of developing Fusion reactors. “Numerical plasma physics models are used to improve our understanding of transport, instability growth and other poorly understood phenomena encountered in the experimental devices edging toward viable fusion energy. Since computational expense imposes a major limitation on accurate physical modeling, computational resources must be used as efficiently as possible.”

Interview: DDN’s Jessica Popp on the Importance of Diversity in HPC

In this video, ISC Diversity Chair Kim McMahon interviews Jessica Popp from DDN about the importance of fostering diversity in High Performance Computing. “Through collaboration and networking, the Women in HPC community strives to bring together women in HPC and technical computing while encouraging women to engage in outreach activities and improve the visibility of inspirational role models.”

Agenda Posted: Hot Interconnects Conference in Santa Clara

The Hot Interconnects conference has posted their program Agenda. The event takes place Aug. 28-30 in Santa Clara, California. “Join us for our 25th year of an information-packed three-day Symposium about the latest in High Performance Interconnects. IEEE Hot Interconnects is the premier international forum for researchers and developers of state-of-the-art hardware and software architectures and implementations for interconnection networks of all scales, ranging from multi-core on-chip interconnects to those within systems, clusters, and data centers. Leaders in industry and academia attend the conference to interact with individuals at the forefront of this field.”

Lenovo Gains Momentum in HPC at ISC 2017

In this video from ISC 2017, Rick Koopman from Lenovo describes the company’s innovative solutions for HPC. “Lenovo recently announced the delivery of one of the most powerful systems – among the first in the world based on Intel Xeon Platinum processor family – to Barcelona Supercomputing Center (BSC). The BSC MareNostrum 4 supercomputer, tasked with jobs in science and engineering research, incorporates 48 racks with more than 3,400 nodes with next generation Intel Xeon processors and a central memory of 390 Terabytes. Its peak power will be over 11 Petaflops.”

Panel Discussion: Sustainable Software Development in Computational Sciences

“PASC has recently formed collaborative partnerships with a number of scientific journals. In this panel discussion, representatives from these journals are invited to express their thoughts regarding publication practices in the computational sciences, including the publication of software codes. How can we validate published results and guarantee reproducibility? Finally, we will describe our vision for the PASC papers initiative going forward.”