Hot Interconnect 2012 Presentation Videos

insideHPC provided onsite coverage of Hot Interconnects 2012 in Santa Clara.

• George Papen presents: Hybrid Datacenter Networks.
• Caliper – Precise and Responsive Traffic Generator

• Posted: 2012-08-27 01:02:28 UTC

  In this video, Yashar Ganjali from the University of Toronto presents: Caliper – Precise and Responsive Traffic Generator. “This paper presents Caliper, a highly-accurate packet injection tool that generates precise and responsive traffic. Caliper takes live packets generated on a host computer and transmits them onto a gigabit Ethernet network with precise inter-transmission times. Existing software traffic generators rely on generic Network Interface Cards which, as we demonstrate, do not provide high-precision timing guarantees. Hence, performing valid and convincing experiments becomes difficult or impossible in the context of time-sensitive network experiments. Our evaluations show that Caliper is able to reproduce packet inter-transmission times from a given arbitrary distribution while capturing the closed-loop feedback of TCP sources. ” Recorded at the Hot Interconnects 2012 conference in Santa Clara. http://hoti.org

• Weighted Differential Scheduler

  Posted: 2012-08-27 00:58:48 UTC

  In this video, Hans Eberle from Oracle Labs presents: Weighted Differential Scheduler. “The Weighted Differential Scheduler (WDS) is a new scheduling discipline for accessing shared resources. The work described here was motivated by the need for a simple weighted scheduler for a network switch where multiple packet flows are competing for an output port. The scheme can be implemented with simple arithmetic logic and finite state machines. We are describing several versions of WDS that can merge two or more flows. An analysis reveals that WDS has lower jitter than any other weighted scheduler known to us.” Recorded at the Hot Interconnects Conference 2012 in Santa Clara. http://hoti.org

• Performance Analysis of InfiniBand FDR and 40GigE RoCE on HPC and Cloud Computing Systems

  Posted: 2012-08-26 17:03:43 UTC

  In this video, Jerome Vienne from Ohio State University presents: Performance Analysis and Evaluation of InfiniBand FDR and 40GigE RoCE on HPC and Cloud Computing Systems. “In this paper, we evaluate various high performance interconnects over the new PCIe Gen3 interface with HPC as well as cloud computing workloads. Our comprehensive analysis, done at different levels, provides a global scope of the impact these modern interconnects have on the performance of HPC applications and cloud computing middlewares. The results of our experiments show that the latest InfiniBand FDR interconnect gives the best performance for HPC as well as cloud computing applications.” Recorded at Hot Interconnects 2012 in Santa Clara. http://hoti.org

• Networks: How to Compare Alternative Architectures

  Posted: 2012-08-27 23:22:05 UTC

  In this video, Radia Perlman from Intel presents: How to Compare Alternative Architectures. “There are various aspects of network infrastructure that are orthogonal, and therefore can be compared conceptually. For example, the syntax of encapsulation, how forwarding tables are calculated, and whether forwarding tables are filled in proactively, or on-demand when a new flow starts. This talk will explain these concepts, and show how various proposed architectures (such as TRILL, VXLAN, OpenFlow, etc. compare.)” Recorded at the Hot Interconnects 2012 Conference. http://hoti.org http://hoti.org

• Call for Participation in Small Business Technology Transfer (STTR)

  Posted: 2012-08-26 17:22:42 UTC

  Got Exascale ideas? In this video, Thomas Ndousse-Fetter from the DoE Department of Science announces a Call for Participation in the Small Business Innovation Research (SBIR) and Small Business Technology Transfer (STTR) programs. The program is for small businesses that want to get involved in the Exascale technology development ecosystem. “A Technology Transfer Opportunity (TTO) is an opportunity to leverage technology that has been developed at a DOE National Laboratory. Each TTO will be described in a particular subtopic and additional information may be obtained by using the link in the subtopic to the DOE National Laboratory that has developed the technology. Typically the technology was developed with DOE funding of either basic or applied research at a DOE National Laboratory and is available for transfer to the private sector. The level of technology maturity will vary and applicants are encouraged to contact the appropriate Laboratory prior to submitting an application.” Learn more about the program at: http://science.energy.gov/sbir/ Recorded at the Hot Interconnects 2012 Conference. http://hoti.org

• Power-Efficient, High-Bandwidth Optical Interconnects for High Performance Computing

  Posted: 2012-08-25 16:54:07 UTC

  In this video, Fuad Doany from IBM T. J. Watson presents: Power-Efficient, High-Bandwidth Optical Interconnects for High Performance Computing. “High performance computing systems are driving development and large-scale deployment of parallel optical interconnects to meet the ever-increasing interconnect bandwidth requirements. We have demonstrated generations of chip-scale transceivers, or “Optochips”, with record setting high-speed, high-density, and low-power performance. Optical interconnects and Si-photonic communication still present significant technical challenges for future exa-scale supercomputers. Optical interconnect technology must continue to evolve to meet future bandwidth demand, including order of magnitude improvements in cost, power, density, and reliability. Integrated low-power parallel transceivers, optical printed circuit boards and silicon based integrated photonics are potential technologies to meet these challenges.” Recorded at the Hot Interconnects 2012 Conference. http://hoti.org

• Electronic-Photonic Integration within Switches and Routers

  Posted: 2012-08-25 15:35:36 UTC

  In this video, Michael R. Watts from MIT presents: Electronic-Photonic Integration within Switches and Routers. “We review recent successes in silicon photonics and how the new capabilities afforded by silicon photonics will impact future Ethernet, Infiniband, and ultimately optical domain switches and routers. Specifically, we consider the impact silicon photonics can have on the cost, bandwidth, radix, and power consumption scaling of future switches and routers.” Recorded at the Hot Interconnects 2012 conference in Santa Clara. http://hoti.org

• How SDNs Will Tame Networks

  Posted: 2012-08-25 20:04:39 UTC

  In this video, Nick McKeown from Stanford presents: How SDNs Will Tame Networks. “Networks are notoriously hard to debug. Today, we only have a rudimentary set of tools available, such as ping, traceroute, tcpdump, and netflow. These tools try to reconstruct the distributed state of the network in an ad-hoc fashion, while the state is being constantly changed by a variety of complex distributed protocols. Software-Defined Networks (SDNs) make it possible – for the first time – to verify, validate, and even prove that the network is behaving correctly. SDN provides the opportunity to rethink how we write network control programs, from the development of control programs all the way to their deployment in production networks.” Recorded at the Hot Interconnects 2012 conference in Santa Clara. http://hoti.org

• Cray High Speed Networking

  Posted: 2012-08-25 08:11:01 UTC

  In this video, Cray’s Bob Alverson presents: Cray High Speed Networking. “This talk gives an overview of high speed interconnects across all of Cray’s products. Going back to the Seastar router, Cray has a torus network with high bandwidth. When combined with massively multithreading technology in uRiKA, Seastar provides direct load and store support that is unmatched today using commodity processors, especially on Big Data graph problems. The Gemini router introduced support for fine-grained load and store without requiring a custom processor. Our next generation router, known as Aries, brings that technology to the PCI Express bus, so that it can operate with a much wider range of processors. With Aries, the network topology is revamped to take best advantage of fiber optic links, which much be used for all but the shortest connections. The result is the dragonfly technology, providing high neighbor bandwidth to a large group of processors and configurable global bandwidth for system wide communication.” Learn more at: http://hoti.org

• The Future Of Network Technology – What is Old, is New Again

  Posted: 2012-08-27 10:40:28 UTC

  In this video, the Hot Interconnects 2012 conference kicks off with a keynote by John Roese, VP and General Manager of Futurewei, Huawei’s North American R&D organization. “Cloud, SDN, Big data, Mobility, BYOD, etc… We are currently in an industry filled with major new technologies and architectures and each of them looks like a green field of innovation. The problem is that we have been here before many times. Our industry operates in cycles and many of the challenges we are taking on technically today at a component, system and solutions level are not as new as we like to think. As the former CTO or Nortel, Broadcom ENG, Enterasys and Cabletron over the past 20 years, I have seen these cycles and hopefully learnt some lessons. This talk will attempt to call out some of the similarity of current technical challenges with past technology work and industry efforts (some succeeded and some failed) in an effort to remind us all of our past experiences and hopefully use that history to better navigate the current challenges.” Learn more at: http://hoti.org

• The OpenOnload User-level Network Stack

  Posted: 2012-08-23 15:07:21 UTC

  In this video, Dave Parry from SolarFlare presents: The OpenOnload User-level Network Stack. “This talk presents the OpenOnload architecture for user-level networking, which is rapidly becoming the de-facto standard for user-space protocol processing of TCP and UDP particularly in latency sensitive applications for the financial markets. We describe our solutions to the challenges outlined above, performance measurements and real world deployment-cases.” Learn more at http://solarflare.com and http://hoti.org

• Rx Stack Accelerator for 10 GbE Integrated NIC

  Posted: 2012-08-23 06:45:23 UTC

  In this video, IBM’s François Abel presents: Rx Stack Accelerator for 10 GbE Integrated NIC. Recorded at the Hot Interconnects 2012 conference in Santa Clara. “This paper describes the design of an integrated accelerator to offload computation intensive protocol-processing tasks. The accelerator combines the concepts of the transport-triggered architecture with a programmable finite-state machine to deliver high instruction-level parallelism, efficient multiway branching and flexibility. The flexibility is key to adapt to protocol changes and address new applications.” Learn more at: http://hoti.org

• A Low-Latency Library in FPGA Hardware for High-Frequency Trading

  Posted: 2012-08-24 15:02:43 UTC

  In this video, John Lockwood from Alto-Logic presents: A Low-Latency Library in FPGA Hardware for High-Frequency Trading (HFT). Recorded at the Hot Interconnects 2012 conference in Santa Clara. “Current High-Frequency Trading (HFT) platforms are typically implemented in software on computers with high-performance network adapters. The high and unpredictable latency of these systems has led the trading world to explore alternative “hybrid” architectures with hardware acceleration. In this paper, we describe how FPGAs are being used in electronic trading to approach the goal of zero latency. We present an FPGA IP library which implements networking, I/O, memory interfaces and financial protocol parsers. The library provides pre-built infrastructure which accelerates the development and verification of new financial applications. We have developed an example financial application using the IP library on a custom 1U FPGA appliance. The application sustains 10Gb/s Ethernet line rate with a fixed end-to-end latency of 1μ – up to two orders of magnitude lower than comparable software implementations.” Learn more at: http://hoti.org

• ParaSplit: A Scalable Architecture on FPGA for Terabit Packet Classification Posted: 2012-08-22 23:55:38 UTC.
• In this video, Jeffrey Fong presents: ParaSplit: A Scalable Architecture on FPGA for Terabit Packet Classification. Recorded at the Hot Interconnects 2012 conference in Santa Clara. “Packet classification is a fundamental enabling function for various applications in switches, routers and firewalls. Due to their performance and scalability limitations, current packet classification solutions are insufficient in addressing the challenges from the growing network bandwidth and the increasing number of new applications. This paper presents a scalable parallel architecture, named ParaSplit, for high-performance packet classification. We propose a rule set partitioning algorithm based on range-point conversion to reduce the overall memory requirement. We further optimize the partitioning by applying the Simulated Annealing technique. We implement the architecture on a Field Programmable Gate Array (FPGA) to achieve high throughput by exploiting the abundant parallelism in the hardware. Evaluation using real-life data sets show that ParaSplit achieves significant reduction in memory requirement, compared with the-state-of-the-art algorithms such as HyperSplit and EffiCuts. Because of the memory efficiency of ParaSplit, our FPGA design can support in the on-chip memory multiple engines, each of which contains up to 10K complex rules. As a result, the architecture with multiple ParaSplit engines in parallel can achieve up to Terabit per second throughput for large and complex rule sets on a single FPGA device.” Learn more at: http://hoti.org