A happy July day to you! Interesting developments took place in the world of HPC-AI notwithstanding the short holiday week (in the U.S.), here’s ….
HPC News Bytes 20250707: The Eye-Popping AI Server Market, the European Quantum Act, TSMC’s Arizona 3nm Fab, EDA for China
July 7, 2025 by
White House Imposing Export Restrictions on EDA Software to China
May 30, 2025 by
The U.S. government’s drive to hobble China’s advanced chip capabilities, mostly focused to date on restricting exports of GPUs used for AI, has spilled over into software used for designing chips – electronic design automation.
Cadence Unveils Millennium M2000 Supercomputer with NVIDIA Blackwell Systems
May 7, 2025 by
SANTA CLARA, Calif.– Cadence today announced the Millennium M2000 Supercomputer featuring NVIDIA Blackwell systems, for AI-basted simulation for engineering and drug design workloads. The supercomputer integrates Cadence’s solvers with NVIDIA HGX B200 systems, NVIDIA RTX PRO 6000 Blackwell Server Edition GPUs and NVIDIA CUDA-X libraries and solver software. Cadence said this combination reduces simulation run times and up to […]
Cadence Announces DDR5 12.8Gbps MRDIMM Gen2 Memory IP System for Cloud AI
April 21, 2025 by
SAN JOSE, Calif.— Cadence (Nasdaq: CDNS) today announced what it said is the industry’s first DDR5 12.8Gbps MRDIMM Gen2 memory IP system solution on the TSMC N3 process. The new solution addresses the need for greater memory bandwidth to accommodate AI processing demands in enterprise and data center applications, including AI in the cloud. The […]
Rapidus Collaborates with Cadence on 2nm Semiconductor Solutions for HPC-AI
December 11, 2024 by
TOKYO, SEMICON Japan, Dec. 10, 2024—Rapidus Corporation, a manufacturer of advanced logic semiconductors, today announced a collaboration with Cadence Design Systems, Inc. to provide co-optimized AI-driven reference design flows and a broad IP portfolio. The new collaboration will support the Rapidus 2nm gate-all-around (GAA) process and leverage the design and manufacturing benefits from its backside power delivery […]
Cadence and Intel Foundry Partner on EMIB Packaging for Heterogeneous Integration
February 21, 2024 by
Feb. 21, 2024 — EDA software company Cadence and Intel Foundry have collaborated to develop an integrated advanced packaging flow utilizing Embedded Multi-die Interconnect Bridge (EMIB) technology to address the complexity in heterogeneously integrated multi-chip(let) architectures, the companies announced. The collaboration enables Intel customers to leverage advanced packaging to accelerate the high-performance computing (HPC), AI […]
HPC News Bytes 20240212: Honda Taps Cadence CFD HPC, Chip Industry Gyrations, Yelick in ISC Spotlight
February 12, 2024 by
Good day-after-Super-Bowl morning to you! It was an interesting week in HPC-AI last week, here’s a quick (5:47) run through some of the latest goings on: Honda taps Cadence supercomputer for air taxi R&D, chip industry gyrations, Kathy Yelick to deliver ISC 2024 keynote, Google settles patent infringement case….
Cadence Announces AI-Driven EDA Verification Platform
September 13, 2022 by
SAN JOSE, Calif.— Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced the Cadence Verisium AI-driven verification platform, a suite of applications leveraging big data and AI designed to optimize verification workloads, boost coverage and accelerate root cause analysis of bugs. The Verisium platform is built on the new Cadence Joint Enterprise Data and AI (JedAI) […]
Cadence Supports Intelligent SoC Development with On-Device Tensilica AI Platform
September 13, 2021 by
SAN JOSE, Calif., September 13, 2021—Cadence Design Systems, Inc. (Nasdaq: CDNS) today unveiled its Tensilica AI Platform for AI SoC development, including three supporting product families optimized for varying data and on-device AI requirements. Spanning the low, mid and high end, the platform delivers scalable and energy-efficient on-device to edge AI processing, which is key […]
Cadence and TSMC Advance Towards 7nm FinFET Designs
September 23, 2016 by
Today Cadence Design Systems announced several important deliveries in its collaboration with TSMC to advance 7nm FinFET designs for mobile and high-performance computing platforms. Working together, Cadence and TSMC have developed some of the first design IP offerings for the 7nm process, offering early IP access to protocols that are optimized for and most relevant to mobile and HPC applications.
