“Modern systems will continue to grow in scale, and applications must evolve to fully exploit the performance of these systems. While today’s HPC developers are aware of code modernization, many are not yet taking full advantage of the environment and hardware capabilities available to them. Intel is committed to helping the HPC community develop modern code that can fully leverage today’s hardware and carry forward to the future. This requires a multi-year effort complete with all the necessary training, tools and support. The customer training we provide and the initiatives and programs we have launched and will continue to create all support that effort.”
Hewlett Packard Enterprise Showcases Benefits of Code Modernization
December 3, 2015 by
“We’ve tailored our story for the HPC developers here, who are really worried about applications and performance of applications. What’s really happened traditionally is that the single-threaded applications had not really been able to take advantage of the multi-core processor-based server platforms. So they’ve not really been getting the optimized platform and they’ve been leaving money on the table, so to speak. Because when you can optimize your applications for parallelism, you can take advantage of these multi-processor server platform. And you can get sometimes up to 10x performance boost, maybe sometime 100x, we’ve seen some financial services applications, or 3x for chemistry types of simulations as an example.”
Who Will Write Next-generation Software?
November 23, 2015 by
In this special guest feature from Scientific Computing World, Robert Roe writes that software scalability and portability may be more important even than energy efficiency to the future of HPC. “As the HPC market searches for the optimal strategy to reach exascale, it is clear that the major roadblock to improving the performance of applications will be the scalability of software, rather than the hardware configuration – or even the energy costs associated with running the system.”
Podcast: Intel HPC Developer Conference Coming to Austin for SC15
October 22, 2015 by
In this podcast, Intel Software Evangelist James Reinders describes the upcoming Intel HPC Developer Conference. Featuring a keynote by Jack Dongarra from the University of Tennessee, the event takes place Nov. 14-15 in Austin, just prior to SC15. “Modernizing your code on Intel architecture can help you achieve breakthrough performance for highly parallel applications. And, you won’t have to recode your entire problem, or master new tools and programming models.”
Video: NOAA Software Engineering for Novel Architectures (SENA) Project
October 2, 2015 by
“NOAA will acquire software engineering support and associated tools to re-architect NOAA’s applications to run efficiently on next generation fine-grain HPC architectures. From a recent procurement document: “Finegrain architecture (FGA) is defined as: a processing unit that supports more than 60 concurrent threads in hardware (e.g. GPU or a large core-count device).”
XSEDE & UC Berkeley Offer Online Parallel Computing Course
September 2, 2015 by
The XSEDE project and the University of California, Berkeley are offering an online course on parallel computing for graduate students and advanced undergraduates.
Experts Focus on Code Efficiency at ISC 2015
August 24, 2015 by
In this special guest feature, Robert Roe from Scientific Computing World explores the efforts made by top HPC centers to scale software codes to the extreme levels necessary for exascale computing. “The speed with which supercomputers process useful applications is more important than rankings on the TOP500, experts told the ISC High Performance Conference in Frankfurt last month.”
Titan Supercomputer Powers the Future of Forecasting
August 22, 2015 by
Knowing how the weather will behave in the near future is indispensable for countless human endeavors. Now, researchers at ECMWF are leveraging the computational power of the Titan supercomputer at Oak Ridge to improve weather forecasting.
Training the Next Generation of Code Developers for HPC – Part 2
August 17, 2015 by
This is the second article in a two-part series about the challenges facing the HPC community in training people to write code and develop algorithms for current and future, massively-parallel, massive-scale HPC systems.
Colfax to Offer Free Online Training for Intel Code Modernization
August 13, 2015 by
Today Colfax International announced free online workshops on parallel programming and optimization for Intel architecture, including Intel Xeon processors and Intel Xeon Phi coprocessors. “The Hands-on Workshop (HOW) series will introduce best practices to researchers and developers to efficiently extract maximum performance out of modern parallel processors, achieving shorter time to solution, higher research productivity, and future-proof design.”
