Preparing for Advanced Manycore Architectures – and Implications on the Interconnect

In this video from the 2015 OFS Developer’s Workshop, Katie Antypas from LBNL describes preparations for the Cori supercomputer. “We need to emphasize here that the Knights Landing processor is self-hosted, and so that means it’s not an accelerator. It’s not a coprocessor and the particular kernel processor that will be having for NERSC-8, will have more than 60 cores and it will have multiple hardware threads for the core. That’s a lot, right? Having 60 cores per node with multiple hardware threads. That a significant increase from both our Hopper and Edison system, which has 24 cores each.”

Video: Preparing Your Application for Advanced Manycore Architectures

“Confronting power limitations and the high cost of data movement, new supercomputing architectures within the DOE are requiring users make changes to application codes to achieve high performance. More specifically, users will need to exploit greater on-node parallelism and longer vector units, and restructure code to take advantage of memory locality. In this presentation you will learn about coming architectural trends and what you can do now to start preparing your application.”

NERSC Leads Next-Generation Code Optimization Effort

“We are excited about launching NESAP in partnership with Cray and Intel to help transition our broad user base to energy-efficient architectures,” said Sudip Dosanjh, director of NERSC, the primary HPC facility for the DOE’s Office of Science. “We expect to see many aspects of Cori in an exascale computer, including dramatically more concurrency and on-package memory. The response from our users has been overwhelming—they recognize that Cori will allow them to do science that can’t be done on today’s supercomputers.”

Interview: Next-Generation Cori Supercomputer Coming to NERSC

“We need to emphasize here that the Knights Landing processor is self-hosted, and so that means it’s not an accelerator. It’s not a coprocessor and the particular kernel processor that will be having for NERSC-8, will have more than 60 cores and it will have multiple hardware threads for the core. That’s a lot, right? Having 60 cores per node with multiple hardware thread. That a significant increase from both our Hopper and Edison system, which has 24 cores each. So we’re going to be working with our users to figure out what’s the right amount of parallelism that they need to expose in their application. That’s one really big difference.”

This Week in HPC: NERSC Buys Knights Landing Supercomputer & Altair’s Bill Nitzberg on Heartbleed and HPC

In this episode of This Week in HPC, Michael Feldman and Addison Snell from Intersect360 Research discuss the new Cori supercomputer that will be deployed at NERSC in 2016. After the break, Altair’s Bill Nitzberg discusses the cluster security implications of the Heartbleed exploit.