March 18, 2021 — DARPA (Defense Advanced Research Projects Agency) today announced the Structured Array Hardware for Automatically Realized Applications (SAHARA) program, which aims to expand access to domestic manufacturing capabilities to tackle challenges hampering the secure development of custom chips for defense systems. Working in partnership with Intel and academic researchers from University of […]
DARPA Announces FPGA-to-ASICs Program with Intel to Expand US-based Chip Making for Defense
March 18, 2021 by Leave a Comment
Intel Developing ASIC Accelerator for DARPA ‘Holy Grail’ Cybersecurity Project
March 8, 2021 by
Intel has joined the U.S. Defense Advanced Research Agency (DARPA) in a fully homomorphic encryption (FHE) program that takes aim at the “holy grail” of cybersecurity – protecting data during processing, when it is most vulnerable to attack. To date, FHE adoption has been slow because FHE methods on cryptograms is data-intensive and incurs a […]
Arm and DARPA Announce 3-Year Development Agreement
August 21, 2020 by
Arm and the U.S. Defense Advanced Research Projects Agency (DARPA) have announced a three-year partnership agreement to “enable the research community that supports DARPA’s programs to quickly and easily take advantage of Arm’s leading IP, tools and support, accelerating innovation in a variety of fields.” Under the auspices of DARPA’s Electronics Resurgence Initiative, the agreement establishes […]
LLNL Researchers aid COVID-19 response in anti-viral research
March 27, 2020 by
Backed by five high performance computing (HPC) clusters and years of expertise in vaccine and countermeasure development, a COVID-19 response team of LLNL researchers from various disciplines has used modeling & simulation, along with machine learning, to identify about 20 initial, yet promising, antibody designs from a nearly infinite set of potentials and to examine millions of small molecules that could have anti-viral properties. The candidates will need to be synthesized and experimentally tested — which Lab researchers cautioned could take time — but progress is being made.
Ayar Labs, DARPA and Intel Replace Electronic I/O with Efficient Optical Signaling
March 25, 2020 by
Researchers from Intel and Ayar Labs working on PIPES have successfully replaced the traditional electrical input/output (I/O) of a state-of-the-art field programmable gate array (FPGA) with efficient optical signaling interfaces. The demonstration leverages an optical interface developed by Ayar Labs called TeraPHY, an optical I/O chiplet that replaces electrical serializer/deserializer (SERDES) chiplets. “FPGAs with photonic interfaces will have broad impact, improving high-performance computing, artificial intelligence, large-scale emulation, and DoD-specific capabilities such as advanced radars.”
Ayar Labs Joins DARPA PIPES Project as Intel Optical IO Provider
November 22, 2019 by
Optical startup Ayar Labs has been selected as Intel’s optical I/O solution partner for their recently awarded DARPA PIPES research project. “The goal of PIPES (Photonics in Package for Extreme Scalability) is to develop integrated optical I/O solutions co-packaged with next generation FPGA/CPU/GPU and accelerators in Multi-Chip Packages (MCP) to provide extreme data rates (input/output) at ultra-low power over much longer distances than supported by current technology. In the first phase of the project, the Ayar Labs TeraPHY chiplet will be co-packaged with an Intel FPGA using the AIB (Advanced Interconnect Bus) interface and Intel’s EMIB silicon-bridge packaging.”
DARPA FastNICs Program Looks to Accelerate Application Performance by 100x
September 28, 2019 by
DARPA is looking to create new networking approaches to accelerate distributed application performance by 100x with the FastNICs program. “FastNICs seeks to improve network stack performance by a factor of 100 through the creation of clean-slate networking approaches. Enabling this significant performance gain will require a rework of the entire network stack – from the application layer through the system software layer, down to the hardware.”
AMD: Delivering the Future of High-Performance Computing
September 6, 2019 by
Dr. Lisa Su from AMD gave this talk at the recent DARPA Electronics Resurgence Initiative Summit. “Optimum system performance requires co-design of silicon chips, system architecture, and software. She presented the example of the Frontier exascale computer system being developed for Oak Ridge National Lab, which should exhibit 1.5 exaflops by 2021. While the highest-performance chips and systems will initially be limited to the most expensive machines, it is expected that similar technology will become available within a few years in data centers, edge computers, and even mobile devices.”
New Funding and DARPA Grant to Propel Optical Interconnects at Ayar Labs
April 30, 2019 by
Today Ayar Labs announced that the company has secured additional funding to fuel its growth as it drives to productize its TeraPHY optical I/O chiplets and SuperNova multi-wavelength lasers in 2019. The company aims to disrupt the traditional performance, cost, and efficiency curves of the semiconductor and computing industries by driving a” 1000x improvement” in interconnect bandwidth density at 10x lower power.
DARPA Selects Research Projects for Next-Gen Processing Technology
August 5, 2018 by
DARPA (Defense Advanced Research Projects Agency) has announced the academic and industry research groups selected to develop new computing technologies to drive computing performance post Moore’s Law. “These projects hope to overcome one of the fundamental performance bottlenecks facing HPC users the ‘memory bottleneck’. By setting researchers the task of investigating vertical, rather than flat or planar integration of microsystem components—as well as new materials, components, and algorithms capable of closing the gap between memory and logic functions—the program managers leading the 3DSoC and FRANC programs hope to create new means of computing vast amounts of information.”
