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DARPA Announces Teams Qualifying for Subterranean Challenge Virtual Competition Finals

Twelve teams have qualified for the DARPA Subterranean (SubT) Challenge Virtual Competition Final Event, to be held September 21-24, where $1.5-million of prizes are at stake. Their algorithms will guide virtual versions of real robots as they drive or fly through unfamiliar simulated underground courses and locate items of interest such as injured survivors, cell phones, backpacks, […]

DARPA Announces Research Teams to Develop Intelligent Event-Based Imagers

July 2, 2021 — DARPA today announced that three teams of researchers led by Raytheon, BAE Systems, and Northrop Grumman have been selected to develop event-based infrared (IR) camera technologies under the Fast Event-based Neuromorphic Camera and Electronics (FENCE) program. Event-based – or neuromorphic – cameras are an emerging class of sensors with demonstrated advantages […]

DARPA Announces FPGA-to-ASICs Program with Intel to Expand US-based Chip Making for Defense

March 18, 2021 — DARPA (Defense Advanced Research Projects Agency) today announced the Structured Array Hardware for Automatically Realized Applications (SAHARA) program, which aims to expand access to domestic manufacturing capabilities to tackle challenges hampering the secure development of custom chips for defense systems. Working in partnership with Intel and academic researchers from University of […]

Intel Developing ASIC Accelerator for DARPA ‘Holy Grail’ Cybersecurity Project

Intel has joined the U.S. Defense Advanced Research Agency (DARPA) in a fully homomorphic encryption (FHE) program that takes aim at the “holy grail” of cybersecurity – protecting data during processing, when it is most vulnerable to attack. To date, FHE adoption has been slow because FHE methods on cryptograms is data-intensive and incurs a […]

Arm and DARPA Announce 3-Year Development Agreement

Arm and the U.S. Defense Advanced Research Projects Agency (DARPA) have announced a three-year partnership agreement to “enable the research community that supports DARPA’s programs to quickly and easily take advantage of Arm’s leading IP, tools and support, accelerating innovation in a variety of fields.” Under the auspices of DARPA’s Electronics Resurgence Initiative, the agreement establishes […]

LLNL Researchers aid COVID-19 response in anti-viral research

Backed by five high performance computing (HPC) clusters and years of expertise in vaccine and countermeasure development, a COVID-19 response team of LLNL researchers from various disciplines has used modeling & simulation, along with machine learning, to identify about 20 initial, yet promising, antibody designs from a nearly infinite set of potentials and to examine millions of small molecules that could have anti-viral properties. The candidates will need to be synthesized and experimentally tested — which Lab researchers cautioned could take time — but progress is being made.

Ayar Labs, DARPA and Intel Replace Electronic I/O with Efficient Optical Signaling

Researchers from Intel and Ayar Labs working on PIPES have successfully replaced the traditional electrical input/output (I/O) of a state-of-the-art field programmable gate array (FPGA) with efficient optical signaling interfaces. The demonstration leverages an optical interface developed by Ayar Labs called TeraPHY, an optical I/O chiplet that replaces electrical serializer/deserializer (SERDES) chiplets. “FPGAs with photonic interfaces will have broad impact, improving high-performance computing, artificial intelligence, large-scale emulation, and DoD-specific capabilities such as advanced radars.”

Ayar Labs Joins DARPA PIPES Project as Intel Optical IO Provider

Optical startup Ayar Labs has been selected as Intel’s optical I/O solution partner for their recently awarded DARPA PIPES research project. “The goal of PIPES (Photonics in Package for Extreme Scalability) is to develop integrated optical I/O solutions co-packaged with next generation FPGA/CPU/GPU and accelerators in Multi-Chip Packages (MCP) to provide extreme data rates (input/output) at ultra-low power over much longer distances than supported by current technology. In the first phase of the project, the Ayar Labs TeraPHY chiplet will be co-packaged with an Intel FPGA using the AIB (Advanced Interconnect Bus) interface and Intel’s EMIB silicon-bridge packaging.”

DARPA FastNICs Program Looks to Accelerate Application Performance by 100x

DARPA is looking to create new networking approaches to accelerate distributed application performance by 100x with the FastNICs program. “FastNICs seeks to improve network stack performance by a factor of 100 through the creation of clean-slate networking approaches. Enabling this significant performance gain will require a rework of the entire network stack – from the application layer through the system software layer, down to the hardware.”

AMD: Delivering the Future of High-Performance Computing

Dr. Lisa Su from AMD gave this talk at the recent DARPA Electronics Resurgence Initiative Summit. “Optimum system performance requires co-design of silicon chips, system architecture, and software. She presented the example of the Frontier exascale computer system being developed for Oak Ridge National Lab, which should exhibit 1.5 exaflops by 2021. While the highest-performance chips and systems will initially be limited to the most expensive machines, it is expected that similar technology will become available within a few years in data centers, edge computers, and even mobile devices.”