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Gidel Launches Lossless Compression IP that Reduces FPGA Power Consumption

Today Gidel announced a new compression IP and a renewed focus on compression and encryption algorithms for the HPC and Vision markets. The compression algorithm requires extremely low power, encoding more than 1 GB/sec utilizing just 1% of the FPGA, thus opening up new possibilities for data centers in particular. “Real-time compression capability provides a number of advantages in storage and efficiency,” notes Ofer Pravda, VP Marketing & Sales at Gidel. “Compressed data can be stored in real-time, as opposed to systems that store the raw data and then compress offline at a later date.”

Gidel Launches Acceleration Boards Based on Intel Stratix 10 FPGAs

Today Gidel launched their Proc10S family of high performance, scalable compute acceleration boards. The devices are based on the Stratix 10 FPGA, which was released by Intel in late 2016. “Gidel’s newest acceleration board was designed with high density Big Data and HPC applications in mind. “The Proc10S is a heavy-duty FPGA and thus opens new markets in HPC for Gidel, such as Deep Learning and Big Data analytics,” says Ofer Pravda, VP Marketing and Sales at Gidel. “Gidel’s long history in algorithm acceleration utilizing FPGA technology has resulted in an enormous wealth of product knowledge that provides us with an advantage in certain HPC and Vision arenas.”

Gidel FPGA Tools Speed Development with Intel’s HLS

Today Gidel announced the availability of new development tools that take advantage of Intel’s HLS, producing a speed increase of 5x over prior development options. Intel’s High Level Synthesis (HLS) compiler turns untimed C++ into Register Transfer Level (RTL) — a low- level FPGA code. Gidel’s development tools map board resources to application needs, and provide the glue between the host computer and the FPGA logic by building an Application Support Package (ASP). Gidel’s tools provide access for software developers to be able to work with HLS, and simplify integration of new IP that may utilize HLS into existing designs.