HPC News Bytes 20240212: Honda Taps Cadence CFD HPC, Chip Industry Gyrations, Yelick in ISC Spotlight

Good day-after-Super-Bowl morning to you! It was an interesting week in HPC-AI last week, here’s a quick (5:47) run through some of the latest goings on: Honda taps Cadence supercomputer for air taxi R&D, chip industry gyrations, Kathy Yelick to deliver ISC 2024 keynote, Google settles patent infringement case….

@HPCpodast: Supercomputing Strategists Look out 20 Years at the Post-Exascale HPC Future

Post-exascale supercomputing for the NNSA (National Nuclear Security Administration) is the subject of a new report by a distinguished review committee comprised of notable supercomputing experts, three of whom presented their findings at a webinar last week. Among other observations Shahin and Doug came away with is that those responsible for guiding U.S. supercomputing leadership on the global stage are under relentless pressure, in an increasingly challenging environment, to make mistake-free, long-term strategic choices. Their task is like that of Sisyphus, except the boulder never rolls down the mountain, it must eternally be pushed up. As one of the panelists — Dan Reed of the University of Idaho — said, “in supercomputing, these are the best of times and the worst of times.”

@HPCpodcast: UC Berkeley’s and LBNL’s Kathy Yelick on Exascale, the Future of Supercomputing, Partitioned Global Address Space and Diversity in HPC

Today, on the eve of Exascale Day, the @HPCpodcast is delighted to have Kathy Yelick as our special guest to observe Oct. 18 (1018 – a billion billion calculations per second). Dr. Yelick is the Robert S. Pepper Distinguished Professor of Electrical Engineering and Computer Sciences and the Vice Chancellor for Research at UC Berkeley, and Senior Faculty Scientist at Lawrence Berkeley National Laboratory.