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Video: Virtual RDMA Devices

In this video from the 2015 OFS Developer’s Workshop, Parav Pandit from Emulex presents: Virtual RDMA Devices.

Video: Rapid I/O Update

In this video from the 2015 OFS Developer’s Workshop, Rick O’Connor from Rapid I/O presents: Rapid I/O Update.

Video: Multipath RDMA

The main motivation for Multipath RDMA is to support three types of features: Failovers and High Availability Support, Bandwidth Aggregation, and L3 datacenter support.

HPC News Roundup for March 27, 2015

I’m on my way home from a series of Springtime HPC conferences with boatload of new videos and interviews on the latest in high performance computing. Here are some notable items that may have not made it to the front page.

Internet of Things & What it Means to Fabrics

In this video from the 2015 OFS Developer’s Workshop, Guy Ailee from Intel presents: Internet of Things & What it Means to Fabrics.

Microsoft Update on RDMA

In this video from the 2015 OFS Developer’s Workshop, Tom Talpey from Microsoft presents: Microsoft Update on RDMA.

Video: OFA Update by ORNL

Watch to get the latest on the Coral supercomputer coming to ORNL. “ORNL’s supercomputing program has grown from humble beginnings to deliver some of the most powerful systems in the world. On the way, it has helped researchers deliver practical breakthroughs and new scientific knowledge in climate, materials, nuclear science, and a wide range of other disciplines.”

Video: Prototyping Byte-Addressable NVM Access

In this video from the 2015 OFS Developer’s Workshop, Bernard Metzler presents: Prototyping Byte-Addressable NVM Access.

Video: A Taste of OFI OpenFabrics Interfaces

In this video from the 2015 OFS Developer’s Workshop, Sean Hefty from Intel presents: A Taste of OFI OpenFabrics Interfaces.

Preparing for Advanced Manycore Architectures – and Implications on the Interconnect

In this video from the 2015 OFS Developer’s Workshop, Katie Antypas from LBNL describes preparations for the Cori supercomputer. “We need to emphasize here that the Knights Landing processor is self-hosted, and so that means it’s not an accelerator. It’s not a coprocessor and the particular kernel processor that will be having for NERSC-8, will have more than 60 cores and it will have multiple hardware threads for the core. That’s a lot, right? Having 60 cores per node with multiple hardware threads. That a significant increase from both our Hopper and Edison system, which has 24 cores each.”