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Mateo Valero on how RISC-V can play a major role in New Supercomputer Architectures

In this eeNews report, Mateo Valero, Director of the Barcelona Supercomputer center, explains how the RISC-V architecture can play a main role in new supercomputer architectures. Valero was the keynote speaker at the recent RISC-V Workshop in Barcelona. “Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.”

BSC to host the RISC-V Workshop on the Road to European Processor Initiative

The Barcelona Supercomputing Center will host the RISC-V Workshop next week, a gathering the open source processor design community to share RISC-V updates, projects and implementations. Founded in 2015, the RISC-V Foundation comprises more than 100 members building the first open, collaborative community of software and hardware innovators powering innovation at the edge forward. BSC is promoting the adoption of RISC-V as a key partner of the European Processor Initiative, the consortium to design and develop Europe’s low-power processors and related technologies for extreme-scale, high-performance computing, which will be funded by the European Commission under the Horizon 2020 program.