In this eeNews report, Mateo Valero, Director of the Barcelona Supercomputer center, explains how the RISC-V architecture can play a main role in new supercomputer architectures. Valero was the keynote speaker at the recent RISC-V Workshop in Barcelona. “Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.”
Mateo Valero on how RISC-V can play a major role in New Supercomputer Architectures
May 10, 2018 by Doug Black
Filed Under: Compute, Events, HPC Hardware, Industry Segments, News, Research / Education, Resources, Videos Tagged With: BSC, RISC-V, RISC-V Workshop
BSC to host the RISC-V Workshop on the Road to European Processor Initiative
May 4, 2018 by staff

The Barcelona Supercomputing Center will host the RISC-V Workshop next week, a gathering the open source processor design community to share RISC-V updates, projects and implementations. Founded in 2015, the RISC-V Foundation comprises more than 100 members building the first open, collaborative community of software and hardware innovators powering innovation at the edge forward. BSC is promoting the adoption of RISC-V as a key partner of the European Processor Initiative, the consortium to design and develop Europe’s low-power processors and related technologies for extreme-scale, high-performance computing, which will be funded by the European Commission under the Horizon 2020 program.
Filed Under: Compute, Events, HPC Hardware, Industry Segments, News, Research / Education, Resources Tagged With: Barcelona Supercomputing Centre, BSC, RISC-V, RISC-V Workshop