In this podcast, the Radio Free HPC team catches up with Calista Redmond, CEO of RISC-V. “RISC-V can be used for light weight tasks such as embedded processing but, on the other hand, is also going to be utilized as the system accelerator for the European Exascale initiative boxes. That’s some serious flexibility.”
How the European Processor Initiative is Leveraging RISC-V for the Future of Supercomputing
August 22, 2019 by
In this special guest feature, Calista Redmond writes that the European Processor Initiative is designing an HPC accelerator based on RISC-V. “The accelerator will be designed for high throughput and power efficiency within the general purpose processor (GPP) chip. The EPI explains that using RISC-V enables the program to leverage “open source resources at [the] hardware architecture level and software level, as well as ensuring independence from non-European patented computing technologies.”
Calista Redmond named CEO of RISC-V Foundation
March 14, 2019 by
Today the RISC-V Foundation announced that Calista Redmond has been appointed Chief Executive Officer (CEO), effective immediately. I’ve always understood the potential short- and long-term impact of the RISC-V license-free ISA on the open source community. Having spent a lot of my career working in the open source ecosystem, I’m excited to help RISC-V grow and deliver on the Foundation’s mission of paving the way for the next 50 years of computing design and innovation,” said Redmond, CEO of the RISC-V Foundation.”
Mateo Valero on how RISC-V can play a major role in New Supercomputer Architectures
May 10, 2018 by
In this eeNews report, Mateo Valero, Director of the Barcelona Supercomputer center, explains how the RISC-V architecture can play a main role in new supercomputer architectures. Valero was the keynote speaker at the recent RISC-V Workshop in Barcelona. “Born in academia and research, RISC-V ISA delivers a new level of free, extensible software and hardware freedom on architecture, paving the way for the next 50 years of computing design and innovation.”
BSC to host the RISC-V Workshop on the Road to European Processor Initiative
May 4, 2018 by
The Barcelona Supercomputing Center will host the RISC-V Workshop next week, a gathering the open source processor design community to share RISC-V updates, projects and implementations. Founded in 2015, the RISC-V Foundation comprises more than 100 members building the first open, collaborative community of software and hardware innovators powering innovation at the edge forward. BSC is promoting the adoption of RISC-V as a key partner of the European Processor Initiative, the consortium to design and develop Europe’s low-power processors and related technologies for extreme-scale, high-performance computing, which will be funded by the European Commission under the Horizon 2020 program.
Radio Free HPC Looks at the European Processor Initiative
March 5, 2018 by
In this podcast, the Radio Free HPC team looks at the European Processor Initiative, an effort to design a build an exascale computer based around European technology. “According to an interview in Primeur Magazine with EPI project coordinator Philippe Notton from Atos, the project involves not only a processor, but an accelerator as well. Will it be based on ARM, OpenPOWER, or something else like RISC-V? We will have to wait and see.”
Realizing Exabyte-scale PM Centric Architectures and Memory Fabrics
February 11, 2018 by
Zvonimir Bandic from Western Digital gave this talk at the SNIA Persistent Memory Summit. “Much has been debated about would it take to scale a system to exabyte main memory with the right levels of latencies to address the world’s growing and diverse data needs. This presentation will explore legacy distributed system architectures based on traditional CPU and peripheral attachment of persistent memory, scaled out through the use of RDMA networking.”
Video: Introduction to RISC-V
March 2, 2016 by
Mellanox announced today that it has joined the RISC-V foundation as a Founding Platinum Sponsor. The RISC-V foundation promotes the open RISC-V instruction set architecture and associated hardware and software ecosystem for a broad range of computing devices.
