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Satoshi Matsuoka Presents: The Inevitable End of Moore’s Law

“The promising new parameter in place of the transistor count is the perceived increase in the capacity and bandwidth of storage, driven by device, architectural, as well as packaging innovations: DRAM-alternative Non-Volatile Memory (NVM) devices, 3-D memory and logic stacking evolving from VIAs to direct silicone stacking, as well as next-generation terabit optics and networks. The overall effect of this is that, the trend to increase the computational intensity as advocated today will no longer result in performance increase, but rather, exploiting the memory and bandwidth capacities will instead be the right methodology.”

Satoshi Matsuoka to Chair ISC 2016 Conference Program

Today ISC Events announced that Prof. Dr. Satoshi Matsuoka of Tokyo Institute of Technology will be the program chairman for ISC 2016. “As the program chair, Dr. Matsuoka will be actively involved in leading the ISC program team to define the ISC 2016 program, especially the focus topics, whilst also working with the steering committee in a multi-year effort to further elevate the value of ISC for the HPC community.”