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Xilinx Alveo U50 Accelerator Cards come to Nimbix Cloud with Broad Application Support

Today Nimbix announced the availability of Xilinx Alveo U50 Accelerator Cards on the Nimbix Cloud. “Nimbix has paved the way for FPGA-accelerated cloud computing and today leads with the broadest portfolio of cloud FPGA solutions in the industry,” said Steve Hebert, CEO of Nimbix. “The availability of U50 accelerators in the Nimbix Cloud and JARVICE XE are helping ISVs and developers bring new applications and solutions to market in the cloud.”

Xilinx Announces Versal Premium ACAP for Network and Cloud Acceleration

Today Xilinx announced Versal Premium, the third series in the Versal ACAP portfolio. The Versal Premium series features highly integrated, networked and power-optimized cores and the industry’s highest bandwidth and compute density on an adaptable platform. Versal Premium is designed for the highest bandwidth networks operating in thermally and spatially constrained environments, as well as for cloud providers who need scalable, adaptable application acceleration.

Xilinx SmartNIC Accelerates Network, Storage, and Compute on Single Device

Today Xilinx announced the industry’s first SmartNIC platform delivering true convergence of network, storage and compute acceleration functions on a single device. “The U25 combines a highly optimized SmartNIC platform with a powerful and flexible FPGA-based engine that supports full programmability and turnkey accelerated applications. The U25 delivers a comprehensive SmartNIC platform to address the industry’s most challenging demands and workloads such as SDN, virtual switching, NFV, NVMe-oF, electronic trading, AI inference, video transcoding, and data analytics.”

Aldec’s new FPGA-based NVMe Data Storage Targets HPC Applications

Today Aldec, Inc. launched a powerful, versatile and time-saving FPGA-based NVMe Data Storage solution to aid in the development of High Performance Computing applications such as High Frequency Trading and Machine Learning. “NVMe SSDs are very popular in a wide range of high-performance computing applications, as are FPGAs because of their ability to handle parallel processing, their speed and programmability, plus the fact MPSoC FPGAs also feature ARM processor cores,” comments Louie De Luna, Director of Marketing. “Our newest FPGA-based embedded solution is aimed at engineers developing systems that will combine the power and benefits of NVMe and FPGAs.”

Accelerate Big Data and HPC applications with FPGAs using JupyterHub

Today InAccel annnounced that it has integrated JupyterHub into the company’s adaptive acceleration platform for FPGAs. InAccel provides an FPGA resource manager that allows the instant deployment, scaling and virtualization of FPGAs making easier than ever the utilization of FPGA clusters for applications like machine learning, data processing, data analytics and many more HPC workloads.

Xilinx Alveo Accelerators Power Real-Time AI-based Intrusion Detection Service

Today Xilinx announced that SK Telecom has adopted Xilinx Alveo Datacenter Accelerator cards to power a real-time AI-based physical intrusion and theft detection service. SK Telecom’s AI inference accelerator (AIX) implemented on Xilinx Alveo cards provides efficient and accurate physical intrusion detection using deep neural networks. “In the era of Artificial Intelligence where new services are being deployed at unprecedented rates, we keep pursuing to innovate our cloud systems to deliver more value to our customers with more reliable and efficient services across diverse segments.”

Codeplay SYCL 1.2.1 Solution offers an Open Alternative to CUDA

Today Codeplay announced the world’s first fully-conformant SYCL 1.2.1 Solution. “As a non-proprietary alternative to the incumbent CUDA, SYCL is an open standard developed by the Khronos Group that enables developers to write code for heterogeneous systems using standard C++. Developers are looking at how they can accelerate their applications without having to write optimized processor specific code. SYCL is the industry standard for C++ acceleration, giving developers a platform to write high-performance code in standard C++, unlocking the performance of accelerators and specialized processors from companies such as AMD, Intel, Renesas and Arm.”

Cortical.io Demonstrates Natural Language Understanding Inspired by Neuroscience

In this video, Cortical.io CEO Francisco Webber demonstrates how the company’s software running on Xilinx FPGAs breaks new ground in the field of natural language understanding (NLU). “Cortical.io delivers AI-based Natural Language Understanding solutions which are quicker and easier to implement and more capable than current approaches. The company’s patented approach enables enterprises to more effectively search, extract, annotate and analyze key information from any kind of unstructured text.”

Exxact Shipping Xilinx Alveo Accelerator-Powered Servers & Workstations

Today Exxact Corporation announced that their Xilinx Alveo Accelerator Powered Workstations & Servers are now shipping worldwide. The Xilinx Alveo accelerator-powered workstations and servers from Exxact are designed to meet the constantly changing needs of the modern data center, providing up to 90X performance increase over CPUs for computationally intensive workloads and perform up to 90X higher than CPUs on key workloads at 1/3 the cost. “Alveo accelerators offers the hardware adaptability of the FPGA with simple high-level development tools as well as containerized deployment options you’ll find with mainstream applications.”

Vitis Unified Software Platform to make FPGA Programming Accessible for All Developers

Since their beginnings, FPGA’s have been notorious for being hard to program. That could be changing with the new Vitis Unified Software Platform from Xilinx.n“Xilinx has created a singular environment that enables programmers and engineers from all disciplines to co-develop and optimize both their hardware and software, using the tools and frameworks they already know and understand. This means that they can adapt their hardware architecture to their application without the need for new silicon.”