Dec. 3, 2024 – Beaverton, Ore. – The CXL Consortium, an industry standard body focused on coherent connectivity, announces the release of its Compute Express Link (CXL) 3.2 Specification. The 3.2 Specification optimizes CXL Memory Device monitoring and management, enhances functionality of CXL Memory Devices for OS and Applications, and extends security with the Trusted Security Protocol (TSP), according to the consortium.
“We are excited to announce the release of the CXL 3.2 Specification to advance the CXL ecosystem by providing enhancements to security, compliance, and functionality of CXL Memory Devices,” said Larrie Carr, CXL Consortium President. “The Consortium continues to develop an open, coherent interconnect and enable an interoperable ecosystem for heterogeneous memory and computing solutions.”
Highlights of the CXL 3.2 Specification:
- CXL Memory Device monitoring and management
- New CXL Hot-Page Monitoring Unit (CHMU) for memory tiering
- Common event record
- Compatibility with PCIe Management Message Pass Through (MMPT)
- CXL online firmware (FW) activation capabilities
- Functionality of CXL Memory Devices for OS and Application
- Post Package Repair (PPR) enhancements
- Additional performance monitoring events for CXL Memory Devices
- Trusted Security Protocol (TSP)
- New Meta-bits Storage Feature for Host-only Coherent Host-Managed Device Memory (HDM-H) address regions
- Improved security by expanding IDE protection
- Increases security of Host-only Coherent Device-Managed Memory with Back-Invalidation (HDM-DB) memory devices
- Enhances compliance tests for interoperability
- Backward compatibility with all previous CXL specifications
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