What is Geneseo?
Geneseo is the codename for an enhancement to PCI Express. Lead by Intel and IBM, this technology will make it easier for co-processor vendors to produce accelerator cards. Among other improvements, Geneseo includes new semantics that reduce the overhead of signaling and synchronization, which makes more efficient interaction between the application software and the accelerator chip.
Intel’s work on Geneseo appears to take aim at blunting AMD’s work on Torrenza, which allows accelerators …
What is stream programming?
A stream is an array whose elements can be operated on in parallel, similar to SIMD computing. In stream programming, data is gathered from memory into a stream, operated on in the stream, and then scattered from the stream back into memory. Memory latency is thus minimized by accessing the data in chunks, similar in effect to caching.
This style of computing was popularized by Stanford’s Merrimac project, which featured the Brook programming language (an …
What are grand challenge problems?
Grand challenge problems refer to really difficult tasks that stretch the limits of cognitive ability. They are especially popular in high technology fields as working towards a solution often yields many new applications. Below are a list of some open problems, along with correlations to previously solved grand challenges.
Prove NP ≠ P
This is the holy grail of anyone working in theoretical computer science. Essentially the class P (set of all languages decidable by a deterministic …
What is Roadrunner?
Not to be confused with Time Warner’s broadband Internet access provider, Roadrunner will be the first supercomputer to use the Cell BE (see earlier post on the PS3 as a cluster node). The unique architecture calls for inclusion of Opteron processors as well, which means that the system will be able to run a broad range of applications. The Cell will be used in much the same way as a co-processor, …
What is software pipelining?
Most computer architectures today are able to execute a few instructions in parallel on a single core by having multiple control and arithmetic-logic units. The order of execution may be scheduled by the compiler (in a VLIW processor) or by the hardware itself (in a superscalar processor). Of course not all instructions can be executed in parallel simply because of dependencies.
Software pipelining, which really has nothing to do with hardware pipelining, is a loop optimization …
