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Podcast: Reducing Complexity with Cluster Management from Bright Computing

In this Conversations in the Cloud podcast, Lee Carter from Bright Computing offers comprehensive software for deploying, managing, and monitoring clustered infrastructure, in the data center or the cloud. “Looking forward, Lee speculates that the future of AI will see new technologies like autonomous cars using complex simulation and modeling in small scale systems, continuing the legacy of HPC.”

How the European Processor Initiative is Leveraging RISC-V for the Future of Supercomputing

In this special guest feature, Calista Redmond writes that the European Processor Initiative is designing an HPC accelerator based on RISC-V. “The accelerator will be designed for high throughput and power efficiency within the general purpose processor (GPP) chip. The EPI explains that using RISC-V enables the program to leverage “open source resources at [the] hardware architecture level and software level, as well as ensuring independence from non-European patented computing technologies.”

Aitken Supercomputer from HPE to Support NASA Moon Missions

A new HPE supercomputer at NASA’s Ames Research Center will run modeling and simulation workloads for lunar landings. The 3.69 Petaflop “Aitken” system is a custom-designed supercomputer that will support modeling and simulations of entry, descent, and landing (EDL) for the agency’s missions and Artemis program, a mission to land the next humans on the lunar South Pole region by 2024.

Video: Xilinx Unveils World’s Largest FPGA

Today Xilinx announced the expansion of its 16 nanometer (nm) Virtex UltraScale+ family to now include the world’s largest FPGA — the Virtex UltraScale+ VU19P. With 35 billion transistors, the VU19P provides the highest logic density and I/O count on a single device ever built, enabling emulation and prototyping of tomorrow’s most advanced ASIC and SoC technologies, as well as test, measurement, compute, networking, aerospace and defense-related applications.

IBM Opens POWER Instruction Set Architecture

This week at The Linux Foundation Open Source Summit, IBM announced it is opening the  POWER Instruction Set Architecture (ISA). “The opening of the Power ISA, an architecture with a long and distinguished history, will help the open hardware movement continue to gain momentum,” said Mateo Valero, Director of Barcelona Supercomputing Center. “BSC, which has collaborated with IBM for more than two decades, is excited that IBM’s announcements today provide additional options to initiatives pursuing innovative new processor and accelerator development with freedom of action.”

Exascale CANDLE Project to Fight Against Cancer

The CANcer Distributed Learning Environment, or CANDLE, is a cross-cutting initiative of the Joint Design of Advanced Computing Solutions for Cancer collaboration and is supported by DOE’s Exascale Computing Project (ECP). CANDLE is building a scalable deep learning environment to run on DOE’s most powerful supercomputers. The goal is to have an easy-to-use environment that can take advantage of the full power of these systems to find the optimal deep-learning models for making predictions in cancer.

Podcast: AMD is Back to Glory Days wit Rome CPU

In this podcast, the Radio Free HPC team looks into the AMD Rome CPU, a beast that brings back the glory days of Opteron and establishes itself as the chip to have, and establishes AMD as the company to beat. After that, they kick off their new regular segment: Henry Newman’s Feel-Good Security Corner.

Frontera: The Next Generation NSF HPC Resource, and Why HPC Still isn’t the Cloud

Dan Stanzione from TACC gave this talk at the MVAPICH User Group. “In this talk, I will describe the main components of the award: the Phase 1 system, “Frontera”, the plans for facility operations and scientific support for the next five years, and the plans to design a Phase 2 system in the mid-2020s to be the NSF Leadership system for the latter half of the decade, with capabilities 10x beyond Frontera. The talk will also discuss the key role MVAPICH and Infiniband play in the project, and why the workload for HPC still can’t fit effectively on the cloud without advanced networking support.”

NetApp EF600 Storage Array Speeds HPC and Analytics

Today NetApp announced the NetApp EF600 storage array. The EF600 is an end-to-end NVMe midrange array that accelerates access to data and empowers companies to rapidly develop new insights for performance-sensitive workloads. “The storage industry is currently transitioning from the SAS to the NVMe protocol, which significantly increases the speed of access to data,” said Tim Stammers, senior analyst, 451 Research. “But conventional storage systems do not fully exploit NVMe performance, because of latencies imposed by their main controllers. NetApp’s E-Series systems were designed to address this architectural issue and are already used widely in performance-sensitive applications. The EF600 sets a new level of performance for the E-Series by introducing end-to-end support for NVMe, and should be considered by IT organizations looking for high-speed storage to serve analytics and other data-intensive applications.”

Intel Talks at Hot Chips gear up for “AI Everywhere”

Today at Hot Chips 2019, Intel revealed new details of upcoming high-performance AI accelerators: Intel Nervana neural network processors, with the NNP-T for training and the NNP-I for inference. Intel engineers also presented technical details on hybrid chip packaging technology, Intel Optane DC persistent memory and chiplet technology for optical I/O. InsideHPC has got all the details, here, all in one place.