Sign up for our newsletter and get the latest HPC news and analysis.
Send me information from insideHPC:


Video: The SX Aurora TSUBASA (Vector Engine)

Deepak Pathania from NEC gave this talk at the HPC User Forum. “The NEC Vector Engine Processor was developed using 16 nm FinFET process technology for extreme high performance and low power consumption. The Vecor Engine Processor has the world’s first implementation of one processor with six HBM2 memory modules using Chip-on-Wafer-on-Substrate technology, leading to the world-record memory bandwidth of 1.2 TB/s.”

Computational Evaluation of Cloud HPC with a Global Atmospheric Model

Daniel Arevalo from DeVine Consulting gave this talk at the HPC User Forum. “Prompted by DoD priorities for modernization, cost savings, and redundancy, this project compared the performance of the NAVGEM on an in-house Cray system against the follow cloud offerings: AWS c4.8xlarge, Penguin B30 queue, Azure H16r, and AWS c5n.18xlarge.”

Applying Cloud Techniques to Address Complexity in HPC System Integrations

Arno Kolster from Providentia Worldwide gave this talk at the HPC User Forum. “OLCF and technology consulting company Providentia Worldwide recently collaborated to develop an intelligence system that combines real-time updates from the IBM AC922 Summit supercomputer with local weather and operational data from its adjacent cooling plant, with the goal of optimizing Summit’s energy efficiency. The OLCF proposed the idea and provided facility data, and Providentia developed a scalable platform to integrate and analyze the data.”

CSCS to Host HPC User Forum in October

CSCS will host the HPC User Forum October 7-8 in Lugano, Switzerland. “It is the first time that CSCS has the pleasure to host the HPC User Forum. The meeting will offer a review of key trends in high-performance computing, with representation of Swiss, European and U.S. perspectives. Special focus will be given to the positioning of Switzerland in the (European) HPC landscape with a presentation by Peter Brönnimann (State Secretariat for Education, Research and Innovation) and by the Director of CSCS, Thomas Schulthess.”

EuroHPC – The European Strategy for Supercomputing

Jean-Marc Denis from EPI gave this talk at the HPC User Forum. “The EuroHPC Joint Undertaking is a 1 billion Euro joint initiative between the EU and European countries to develop a World Class Supercomputing Ecosystem in Europe. EuroHPC will permit the EU and participating countries to coordinate their efforts and share resources with the objective of deploying in Europe a world-class supercomputing infrastructure and a competitive innovation ecosystem in supercomputing technologies, applications and skills.”

Video: The Cray Shasta Architecture

In this video from the HPC User Forum at Argonne, Steve Scott from Cray presents: The Cray Shasta Architecture. The DOE has selected the Shasta architecture to power all three of their planned Exascale systems coming to Argonne, ORNL, and LLNL. “Shasta allows for multiple processor and accelerator architectures and a choice of system interconnect technologies, including our new Cray-designed and developed interconnect we call Slingshot.”

Dr. Dayna Baumeister from Biomimicry to Keynote Altair Technology Conference

Dr. Dayna Baumeister will keynote the 2019 Global Altair Technology Conference (ATC) October 10-11 in Detroit. Baumeister, is co-founder of Biomimicry 3.8, a B-Corp social enterprise that helps clients find innovation inspired by nature and offers the highest level of biomimicry training to professionals worldwide. “Our Global ATC event has become an atmosphere that inspires others who seek inspiration and new ideas to accelerate their organizations as they compete in an increasingly connected world.”

Checkpointing the Un-checkpointable: MANA and the Split-Process Approach

Gene Cooperman from Northeastern University gave this talk at the MVAPICH User Group. “This talk presents an efficient, new software architecture: split processes. The “MANA for MPI” software demonstrates this split-process architecture. The MPI application code resides in “upper-half memory”, and the MPI/network libraries reside in “lower-half memory”.

Identifying Opportunities to Improve Efficiency in HPC Clusters

Jordi Blasco from HPC Now! gave this talk at HPCKP’19. “Jordi Blasco has developed a new open source monitoring tool which allows the HPC user support teams to identify new opportunities to improve the efficiency of the codes being executed on HPC resources. Earlier adopters of this new tool, and through the continuous monitoring of jobs efficiency, have been able to improve the scalability and performance of several codes and workflows.”

AMD: Delivering the Future of High-Performance Computing

Dr. Lisa Su from AMD gave this talk at the recent DARPA Electronics Resurgence Initiative Summit. “Optimum system performance requires co-design of silicon chips, system architecture, and software. She presented the example of the Frontier exascale computer system being developed for Oak Ridge National Lab, which should exhibit 1.5 exaflops by 2021. While the highest-performance chips and systems will initially be limited to the most expensive machines, it is expected that similar technology will become available within a few years in data centers, edge computers, and even mobile devices.”