Today Appentra released Parallelware Trainer 1.4, an interactive, real-time code editor with features that facilitate the learning, usage, and implementation of parallel programming by understanding how and why sections of code can be parallelized. “As Appentra strives to make parallel programming easier, enabling everyone to make the best use of parallel computing hardware from the multi-cores in a laptop to the fastest supercomputers. With this new release, we push Parallelware Trainer further towards that goal.”
Julia Computing and GPU Acceleration
December 13, 2019 by Leave a Comment
Julia is already well regarded for programming multicore CPUs and large parallel computing systems, but recent developments make the language suited for GPU computing as well. The performance possibilities of GPUs can be democratized by providing more high-level tools that are easy to use by a large community of applied mathematicians and machine learning programmers.
Podcast: SCR Scalable Checkpoint/Restart Paves the Way for Exascale
December 8, 2019 by Leave a Comment
A software product called the Scalable Checkpoint/Restart (SCR) Framework 2.0 recently won an R&D 100 Award. In this episode, Elsa Gonsiorowski and Kathryn Mohror of LLNL discuss what SCR does, the challenges involved in creating it, and the impact it is expected to have in HPC. “SCR enables HPC simulations to take advantage of hierarchical storage systems, without complex code modifications. With SCR, the input/output (I/O) performance of scientific simulations can be improved by orders of magnitude.”
Intel’s Kent Moffat describes the exciting new launch of oneAPI
December 4, 2019 by Leave a Comment
In this video, Kent Moffat, senior product manager from Intel, describes the oneAPI initiative, an ambitious shift from today’s single-architecture, single-vendor programming models to a unified, simplified programming model for application development across heterogeneous architectures, including CPUs, GPUs, FPGAs and other accelerators.
Arm HPC User Group Returns to Denver Nov. 18
November 4, 2019 by Leave a Comment
The Arm HPC team invites you to our 5th Annual Arm HPC User Group (AHUG) session at SC19. The all-day event takes place on Monday, Nov. 18 at the Curtis Hotel in Denver. “We have a full day agenda of strategic partners and end-users from all regions of the world sharing their experiences, best practices, plans, ecosystem advances, and results on Arm-based platforms for HPC applications. The goal of this event is, as always, to candidly share and network among the growing number of users and sites that are deploying Arm for HPC and to highlight the work of the many leaders in this area.”
HPC Framework Blocks to Ease Programming of Exascale Supercomputers
October 27, 2019 by Leave a Comment
Researchers are beginning a three-year cross-institute project that aims to lower the barrier to entry for software engineers developing new high-performance applications on large scale parallel systems. “The team of researchers plan to combine user insights, new compiler optimizations, and advanced runtime support to create the PAbB framework which will ultimately create building blocks of parallel code for heterogeneous environments to use across a number of applications from computational science and data science.”
Codeplay SYCL 1.2.1 Solution offers an Open Alternative to CUDA
October 18, 2019 by Leave a Comment
Today Codeplay announced the world’s first fully-conformant SYCL 1.2.1 Solution. “As a non-proprietary alternative to the incumbent CUDA, SYCL is an open standard developed by the Khronos Group that enables developers to write code for heterogeneous systems using standard C++. Developers are looking at how they can accelerate their applications without having to write optimized processor specific code. SYCL is the industry standard for C++ acceleration, giving developers a platform to write high-performance code in standard C++, unlocking the performance of accelerators and specialized processors from companies such as AMD, Intel, Renesas and Arm.”
Vitis Unified Software Platform to make FPGA Programming Accessible for All Developers
October 1, 2019 by Leave a Comment
Since their beginnings, FPGA’s have been notorious for being hard to program. That could be changing with the new Vitis Unified Software Platform from Xilinx.n“Xilinx has created a singular environment that enables programmers and engineers from all disciplines to co-develop and optimize both their hardware and software, using the tools and frameworks they already know and understand. This means that they can adapt their hardware architecture to their application without the need for new silicon.”
Appentra announces Early Access Program for Parallelware Analyzer
September 27, 2019 by Leave a Comment
Today Appentra announced the company is offering developers the opportunity to join the Early Access Program for Parallelware Analyzer. “While Appentra’s Parallelware Trainer provides an interactive learning environment where users can learn how to parallelize, Parallelware Analyzer provides the appropriate tools for the key stages of the parallel development workflow, aiding developers with code analysis that would otherwise be error-prone, time-consuming and completed manually.”
7 Ways HPC Software Developers Can Benefit from Intel Software Investments
September 4, 2019 by Leave a Comment
Intel has long focused on supporting HPC software. But, as the years have gone by, much has changed — and the company’s offerings have grown and evolved. A chapter from a recent edition of Parallel Universe Magazine, from this past July outlines this evolution and offers seven ways HPC software developers can benefit from Intel software investments.
