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Slidecast: HPC and the Cloud – Announcing the Ellexus Container Checker

In this slidecast, Dr. Rosemary Francis describes the new Ellexus Container Checker, a pioneering cloud-based tool that provides visibility into the inner workings of Docker containers. “Container Checker will help people using cloud platforms to quickly detect problems within their containers before they are let loose on the cloud to potentially waste time and compute spend. Estimates suggest that up to 45% of cloud spend is wasted due in part to unknown application activity and unsuitable storage decisions, which is what we want to help businesses tackle.”

Intel Advisor’s TBB Flow Graph Analyzer: Making Complex Layers of Parallelism More Manageable

Some deep learning applications tend to have very complex graphs with thousands of nodes and edges. To make it easier to visualize, analyze, design, and tune such complex parallel applications employing Intel TBB flow graphs, Intel provides Intel Advisor Flow Graph Analyzer (Intel FGA). It gives developers a comprehensive set of tools to examine, debug, and analyze Intel TBB flow graphs.

Ellexus Releases I/O Profiling Tool Suites Based for Arm Architecture

Today Ellexus released versions of its flagship I/O profiling products Breeze, Healthcheck and Mistral, all based on the Arm v8-A architecture. The move comes as part of the company’s strategy to provide cross-platform support that gives engineers a uniform tooling experience across different hardware platforms. “As the high-performance computing industry targets new compute architectures and cloud infrastructures, it’s never been more important to optimise the way programs access large data sets,” said Dr Rosemary Francis, CEO of Ellexus, on the decision to release versions based on Arm. “Bad I/O patterns can harm shared storage and will limit application performance, wasting millions in lost engineering time. We are extremely excited to announce the integration of our tools with the Arm tool suite. Together we will be able to help more organizations to get the most out of their compute clusters.”

Building Fast Data Compression Code with Intel Integrated Performance Primitives (Intel IPP) 2018

Intel® Integrated Performance Primitives (Intel IPP) is a highly optimized, production-ready, library for lossless data compression/decompression targeting image, signal, and data processing, and cryptography applications. Intel IPP includes more than 2,500 image processing, 1,300 signal processing, 500 computer vision, and 300 cryptography optimized functions for creating digital media, enterprise data, embedded, communications, and scientific, technical, and security applications.

Gidel FPGA Tools Speed Development with Intel’s HLS

Today Gidel announced the availability of new development tools that take advantage of Intel’s HLS, producing a speed increase of 5x over prior development options. Intel’s High Level Synthesis (HLS) compiler turns untimed C++ into Register Transfer Level (RTL) — a low- level FPGA code. Gidel’s development tools map board resources to application needs, and provide the glue between the host computer and the FPGA logic by building an Application Support Package (ASP). Gidel’s tools provide access for software developers to be able to work with HLS, and simplify integration of new IP that may utilize HLS into existing designs.

Video: The State of Linux Containers

“Linux Containers gain more and more momentum in all IT ecosystems. This talk provides an overview about what happened in the container landscape (in particular Docker) during the course of the last year and how it impacts datacenter operations, HPC and High-Performance Big Data. Furthermore Christian will give an update/extend on the ‘things to explore’ list he presented in the last Lugano workshop, applying what he learned and came across during the year 2016.”

Intel Compilers 18.0 Tune for AVX-512 ISA Extensions

Intel Compilers 18.0 and Intel Parallel Studio XE 2018 tuning software fully support the AVX-512 instructions. By widening and deepening the vector registers, the new instructions and added enhancements let the compiler squeeze more vector parallelism out of applications than before. Applications compiled with the –xCORE-AVX512 will generate an executable that utilizes these new high-performance instructions.

Visualization in Software using Intel Xeon Phi processors

“Intel has been at the forefront of working with software partners to develop solutions for visualization of data that will scale in the future as many core systems such as the Intel Xeon Phi processor scale. The Intel Xeon Phi processor is extremely capable of producing visualizations that allow scientists and engineers to interactively view massive amounts of data.”

HPC I/O for Computational Scientists

Phil Carns from Argonne gave this talk at the 2017 Argonne Training Program on Extreme-Scale Computing. “Darshan is a scalable HPC I/O characterization tool. It captures an accurate but concise picture of application I/O behavior with minimum overhead. Darshan was originally developed on the IBM Blue Gene series of computers deployed at the Argonne Leadership Computing Facility, but it is portable across a wide variety of platforms include the Cray XE6, Cray XC30, and Linux clusters.  Darshan routinely instruments jobs using up to 786,432 compute cores on the Mira system at ALCF.”

Jesús Labarta from BSC to receive Ken Kennedy Award

Today ACM and IEEE Computer Society named Jesús Labarta of the Barcelona Supercomputing Center as the recipient of the 2017 ACM-IEEE CS Ken Kennedy Award. Labarta is recognized for his seminal contributions to programming models and performance analysis tools for high performance computing. The award will be presented at SC17.