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2020 Predictions from Radio Free HPC

In this podcast, the Radio Free HPC team lays out their tech predictions for 2020. “Henry predicts that we’ll see a RISC-V based supercomputer on the TOP500 list by the end of 2020 – gutsy call on that. This is a double down on a bet that Dan and Henry have, so he’s reinforcing his position. Dan also sees 2020 as the “Year of the FPGA.”

Video: FPGAs and Machine Learning

James Moawad and Greg Nash from Intel gave this talk at ATPESC 2019. “FPGAs are a natural choice for implementing neural networks as they can handle different algorithms in computing, logic, and memory resources in the same device. Faster performance comparing to competitive implementations as the user can hardcore operations into the hardware. Software developers can use the OpenCL device C level programming standard to target FPGAs as accelerators to standard CPUs without having to deal with hardware level design.”

Theta and the Future of Accelerator Programming at Argonne

Scott Parker from Argonne gave this talk at ATPESC 2019. “Designed in collaboration with Intel and Cray, Theta is a 6.92-petaflops (Linpack) supercomputer based on the second-generation Intel Xeon Phi processor and Cray’s high-performance computing software stack. Capable of nearly 10 quadrillion calculations per second, Theta enables researchers to break new ground in scientific investigations that range from modeling the inner workings of the brain to developing new materials for renewable energy applications.”

European Processor Initiative Reaches Important Milestones in First Year

The European Processor Initiative (EPI) has announced the completion of important milestones in its first year. “The first-generation chip family, named Rhea, will include Arm ZEUS architecture general purpose cores and prototypes of high energy-efficient accelerator tiles: RISC-V based (EPAC), Multi-Purpose Processing Array (MPPA), embedded FPGA (eFPGA) and cryptography HW engine. First Rhea chips will be fabricated in N6 technology aiming at the highest processing capabilities and energy efficiency.” Demonstrates Natural Language Understanding Inspired by Neuroscience

In this video, CEO Francisco Webber demonstrates how the company’s software running on Xilinx FPGAs breaks new ground in the field of natural language understanding (NLU). “ delivers AI-based Natural Language Understanding solutions which are quicker and easier to implement and more capable than current approaches. The company’s patented approach enables enterprises to more effectively search, extract, annotate and analyze key information from any kind of unstructured text.”

Leadership Performance with 2nd-Generation Intel Xeon Scalable Processors

According to Intel, its new 2nd generation Intel Xeon Scalable Processor family includes Intel Deep Learning Boost for AI deep learning inference acceleration, fresh features and support for Intel Octane DC (data center) persistent memory, and more. Learn more about the offerings in a new issue of Parallel Universe Magazine.

Intel Ships First 10nm Agilex FPGAs with Integrated Arm Processors

Today Intel announced that it has begun shipments of the first Intel Agilex field programmable gate arrays (FPGAs) to early access program customers. In what may be a surprise to many, the F-Series variant of the chip family also provides the option to integrate a quad-core Arm Cortex-A53 processor to provide high system integration. “Intel FPGAs have provided Microsoft tremendous value for accelerating real-time AI, networking, and other applications/infrastructure across Azure Cloud Services, Bing, and other data center services.”

How the European Processor Initiative is Leveraging RISC-V for the Future of Supercomputing

In this special guest feature, Calista Redmond writes that the European Processor Initiative is designing an HPC accelerator based on RISC-V. “The accelerator will be designed for high throughput and power efficiency within the general purpose processor (GPP) chip. The EPI explains that using RISC-V enables the program to leverage “open source resources at [the] hardware architecture level and software level, as well as ensuring independence from non-European patented computing technologies.”

Xilinx Launches Alveo U50 FPGA Datacenter Accelerator Card

Today Xilinx launched the new Alveo U50 data center accelerator card, the industry’s first low profile adaptable accelerator with PCIe Gen 4 support. Designed for the datacenter, the Alveo U50 is uniquely designed to supercharge a broad range of critical compute, network and storage workloads, all on one reconfigurable platform. “We believe the combination of low-profile form-factor, HBM2 memory performance, and PCIe Gen 4 speed to interface with IBM Power processors will enable the OpenPOWER ecosystem to provide cutting edge adaptable acceleration solutions.” 

Pricing American Options with the NEC SX-Aurora TSUBASA Vector Engine

The Aldwin division of ANEO is now working together with NEC to leverage the leading-edge vector technology of SX-Aurora TSUBASA for porting and optimizing Aldwin’s in-house software for American option pricing. The code is implemented in C++17 and designed to capitalize on the full capabilities of both scalar and vector architectures. It uses OpenMP to multithread the application, while the vectorization is implemented using the Eigen library.