The European Processor Initiative (EPI) has announced the completion of important milestones in its first year. “The first-generation chip family, named Rhea, will include Arm ZEUS architecture general purpose cores and prototypes of high energy-efficient accelerator tiles: RISC-V based (EPAC), Multi-Purpose Processing Array (MPPA), embedded FPGA (eFPGA) and cryptography HW engine. First Rhea chips will be fabricated in N6 technology aiming at the highest processing capabilities and energy efficiency.”
European Processor Initiative Reaches Important Milestones in First Year
November 4, 2019 by Leave a Comment
Cortical.io Demonstrates Natural Language Understanding Inspired by Neuroscience
October 17, 2019 by Leave a Comment
In this video, Cortical.io CEO Francisco Webber demonstrates how the company’s software running on Xilinx FPGAs breaks new ground in the field of natural language understanding (NLU). “Cortical.io delivers AI-based Natural Language Understanding solutions which are quicker and easier to implement and more capable than current approaches. The company’s patented approach enables enterprises to more effectively search, extract, annotate and analyze key information from any kind of unstructured text.”
Leadership Performance with 2nd-Generation Intel Xeon Scalable Processors
September 12, 2019 by Leave a Comment
According to Intel, its new 2nd generation Intel Xeon Scalable Processor family includes Intel Deep Learning Boost for AI deep learning inference acceleration, fresh features and support for Intel Octane DC (data center) persistent memory, and more. Learn more about the offerings in a new issue of Parallel Universe Magazine.
Intel Ships First 10nm Agilex FPGAs with Integrated Arm Processors
August 30, 2019 by 1 Comment
Today Intel announced that it has begun shipments of the first Intel Agilex field programmable gate arrays (FPGAs) to early access program customers. In what may be a surprise to many, the F-Series variant of the chip family also provides the option to integrate a quad-core Arm Cortex-A53 processor to provide high system integration. “Intel FPGAs have provided Microsoft tremendous value for accelerating real-time AI, networking, and other applications/infrastructure across Azure Cloud Services, Bing, and other data center services.”
How the European Processor Initiative is Leveraging RISC-V for the Future of Supercomputing
August 22, 2019 by Leave a Comment
In this special guest feature, Calista Redmond writes that the European Processor Initiative is designing an HPC accelerator based on RISC-V. “The accelerator will be designed for high throughput and power efficiency within the general purpose processor (GPP) chip. The EPI explains that using RISC-V enables the program to leverage “open source resources at [the] hardware architecture level and software level, as well as ensuring independence from non-European patented computing technologies.”
Xilinx Launches Alveo U50 FPGA Datacenter Accelerator Card
August 6, 2019 by Leave a Comment
Today Xilinx launched the new Alveo U50 data center accelerator card, the industry’s first low profile adaptable accelerator with PCIe Gen 4 support. Designed for the datacenter, the Alveo U50 is uniquely designed to supercharge a broad range of critical compute, network and storage workloads, all on one reconfigurable platform. “We believe the combination of low-profile form-factor, HBM2 memory performance, and PCIe Gen 4 speed to interface with IBM Power processors will enable the OpenPOWER ecosystem to provide cutting edge adaptable acceleration solutions.”
Pricing American Options with the NEC SX-Aurora TSUBASA Vector Engine
June 6, 2019 by Leave a Comment
The Aldwin division of ANEO is now working together with NEC to leverage the leading-edge vector technology of SX-Aurora TSUBASA for porting and optimizing Aldwin’s in-house software for American option pricing. The code is implemented in C++17 and designed to capitalize on the full capabilities of both scalar and vector architectures. It uses OpenMP to multithread the application, while the vectorization is implemented using the Eigen library.
EPI delivers first design for high-performance processor
June 4, 2019 by Leave a Comment
The European Processor Initiative (EPI) has delivered its first architectural design to the European Commission and is welcoming new partners. “Energy efficient high-performance families of EPI processors will include most advanced general-purpose and accelerator cores that will deliver unprecedented processing capabilities, enabling EU researchers from academia and industry to most efficiently address global challenges. The business sustainability of the initiative is supported by carefully balanced target markets, with primary focus on exascale HPC/AI and automotive markets.”
GPU Hackathon gears up for Future Perlmutter Supercomputer
May 21, 2019 by Leave a Comment
NERSC recently hosted its first user hackathon to begin preparing key codes for the next-generation architecture of the Perlmutter system. Over four days, experts from NERSC, Cray, and NVIDIA worked with application code teams to help them gain new understanding of the performance characteristics of their applications and optimize their codes for the GPU processors in Perlmutter. “By starting this process early, the code teams will be well prepared for running on GPUs when NERSC deploys the Perlmutter system in 2020.”
NEC-X Opens Vector Engine Data Acceleration Center in Silicon Valley
April 24, 2019 by Leave a Comment
Today NEC-X launched the Vector Engine Data Acceleration Center (VEDAC) at its Silicon Valley facility. This new VEDAC is one of the company’s many offerings to innovators, makers and change agents. The NEC X organization is focused on fostering big data innovations using NEC’s emerging technologies while tapping into Silicon Valley’s rich ecosystem. “We are gratified to see the developing innovations that are taking advantage of the cutting-edge technologies from NEC’s laboratories.”
