Along with his article to be found on this site, technology analyst Adrian Cockcroft of OrionX (and former AWS vice president) joins Shahin and Doug after SC23 to discuss TOP500 trends, the AI-HPC crossover, liquid cooling, chiplets, and the emergence of UCIe and CXL – some of the anticipated advancements are truly eye-popping. In this podcast, sponsored by Lenovo, the relentless pursuit of higher performance, the acceleration in the pace of change in high performance processing, is examined.
@HPCpodcast: Tech Analyst Adrian Cockcroft on Trends Driving Future HPC Architectures
November 30, 2023 by
SC23: TOP500 Trends, the AI-HPC Crossover, Chiplet Standardization, the Emergence of UCIe and CXL Advancements
November 29, 2023 by
By Adrian Cockcroft, Partner & Analyst, OrionX Last year the UCIe chiplet standard had just been launched, and since then just about everyone has joined it, about 130 companies. The idea is that to build a complete CPU or GPU you don’t have to put it all on the same chip from the same….
HPC News Bytes 20231120: SC23 Overview – Exascale Update, New AI Chips, Quantum Village, UCIe-PCIe-Ultra Ethernet
November 20, 2023 by
In this edition of the HPC News Bytes podcast, Shahin takes us on a rapid (5:04) tour of SC23, analyzing the key developments and new technologies that highlighted last week’s conference in Denver: Conference attendance expands to 14,000; exascale update and future; raft of new chips, many focused on AI; Quantum Village at SC23; UCIe, PCIe and Ultra Ethernet
Optical I/O Takes Center Stage at SC23
November 7, 2023 by
[SPONSORED GUEST ARTICLE] Integration of optical I/O with an FPGA is the tip of the iceberg of a new vision to enable new HPC/AI architectural advances through ubiquitous optical interconnects for every piece of compute silicon. If you are attending SC23 November 12-17, be sure to visit Ayar Labs in booth #228 for an exclusive look at the future….
Silicon Photonics and the Hunt for an HPC Bandwidth Bottleneck Breakthrough
December 19, 2022 by
[SPONSORED CONTENT] “FLOPS are cheap, moving data is expensive.” In HPC circles this sentiment is heard often. There’s a growing sense that classical HPC systems and the advanced chips that power them are pushing up against their practical limits, that some foundational new technology is needed to build more balanced systems to achieve the next […]
Avery Design Systems Announces Verification Support for New Chiplet Interconnect Standard
June 15, 2022 by
Tewksbury, MA – June 15, 2022 – Avery Design Systems, a functional verification solutions company, today announced its support for the new UCIe (Universal Chiplet Interconnect Express) standard, providing an efficient approach to enable design and verification engineers to leverage the recently-introduced standard for die-to-die interface connectivity. Avery’s offering includes models and test suites that support […]
Heavyweight UCIe Consortium Launched to Standardize Chiplet Ecosystem
March 2, 2022 by
A consortium of tech industry heavyweights today announced the Universal Chiplet Interconnect Express (UCIe) industry consortium with a mission to establish a die-to-die interconnect standard and foster an open chiplet ecosystem. Founding members include Advanced Semiconductor Engineering, Inc. (ASE), AMD, Arm, Google Cloud, Intel Corporation, Meta, Microsoft Corporation, Qualcomm Incorporated, Samsung, and Taiwan Semiconductor Manufacturing […]
