The European Processor Initiative (EPI) has announced the completion of important milestones in its first year. “The first-generation chip family, named Rhea, will include Arm ZEUS architecture general purpose cores and prototypes of high energy-efficient accelerator tiles: RISC-V based (EPAC), Multi-Purpose Processing Array (MPPA), embedded FPGA (eFPGA) and cryptography HW engine. First Rhea chips will be fabricated in N6 technology aiming at the highest processing capabilities and energy efficiency.”
European Processor Initiative Reaches Important Milestones in First Year
November 4, 2019 by Leave a Comment
Intel Ships First 10nm Agilex FPGAs with Integrated Arm Processors
August 30, 2019 by 1 Comment
Today Intel announced that it has begun shipments of the first Intel Agilex field programmable gate arrays (FPGAs) to early access program customers. In what may be a surprise to many, the F-Series variant of the chip family also provides the option to integrate a quad-core Arm Cortex-A53 processor to provide high system integration. “Intel FPGAs have provided Microsoft tremendous value for accelerating real-time AI, networking, and other applications/infrastructure across Azure Cloud Services, Bing, and other data center services.”
Video: Xilinx Unveils World’s Largest FPGA
August 21, 2019 by 1 Comment
Today Xilinx announced the expansion of its 16 nanometer (nm) Virtex UltraScale+ family to now include the world’s largest FPGA — the Virtex UltraScale+ VU19P. With 35 billion transistors, the VU19P provides the highest logic density and I/O count on a single device ever built, enabling emulation and prototyping of tomorrow’s most advanced ASIC and SoC technologies, as well as test, measurement, compute, networking, aerospace and defense-related applications.
Nimbix Launches HyperHub Catalog of Cloud-enabled Applications
August 15, 2019 by Leave a Comment
Today HPC cloud provider Nimbix announced the launch of HyperHub, a point-and-click catalog of HPC and accelerated applications. With the new self-service marketplace, engineers and scientists can select from a growing ecosystem of prebuilt apps and workflows and run them on any device, cloud, or on-premises infrastructure, anywhere in the world. “By providing access to a growing catalog of consumable, run-anywhere apps, HyperHub enables engineers and scientists to shorten their time-to-value when tackling complex, compute-intensive tasks like simulation and AI. HyperHub’s open marketplace structure also encourages ISVs and partners to continue building and publishing additional high-quality HPC apps for these professionals to use.”
New Texascale Magazine from TACC looks at HPC for the Endless Frontier
March 11, 2019 by Leave a Comment
This feature story describes how the computational power of Frontera will be a game changer for research. Late last year, the Texas Advanced Computing Center announced plans to deploy Frontera, the world’s fastest supercomputer in academia. To prepare for launch, TACC just published the inaugural edition of Texascale, an annual magazine with stories that highlight the people, science, systems, and programs that make TACC one of the leading academic computing centers in the world.
An Introduction to High Performance Computing
January 14, 2019 by Leave a Comment
In this video, Bill Jenkins from Intel presents and introduction to High Performance Computing. “This online training will provide a high-level introduction to high performance computing, the problem it solves and the vertical markets it solves it in. Rather than focusing on the step by step, this training will educate into the concepts and resources available to perform the data analytics process and even also discuss where accelerators can be used.”
How FPGAs Provide Versatile Acceleration for HPE Servers
December 6, 2018 by Leave a Comment
In this video from SC18 in Dallas, Osama Sarfaraz from HPE describes how the company is using Intel FPGA’s to deliver Programmability, Flexibility, and Upgradability for HPC users. “The FPGA is designed to actually be configured by a customer or designer after manufacturing; hence it is “field-programmable.” An FPGA offers high I/O bandwidth plus a fine-grained, flexible and custom parallelism, allowing it to be programmed for many different types of workloads, including Big Data analytics, financial services and deep learning.”
Xilinx Steps Up with Alveo FPGA boards and Versal Adaptive Compute Acceleration Platform
October 3, 2018 by Leave a Comment
Today FPGA maker Xilinx unveiled Versal, “the industry’s first adaptive compute acceleration platform (ACAP)”. The company also announced new Alveo FPGA cards, which the company claims can deliver “4X the performance of GPUs, 90X the performance of CPUs, plus unprecedented adaptability across workloads.” AMD, one of the Xilinx partners that is showcasing products based on the new Alveo boards, announced a server that will set a new world record for real-time AI inference processing, with a mind-boggling 30,000-images-per-second inference throughput.
Intel Beefs up FPGA Line
September 25, 2018 by Leave a Comment
Today Intel introduced the Intel Programmable Acceleration Card (PAC) with Intel Stratix 10 SX FPGA. The card leverages the Acceleration Stack for Intel Xeon CPU with FPGAs, providing data center developers a robust platform to deploy FPGA-based accelerated workloads.
Gidel Launches Lossless Compression IP that Reduces FPGA Power Consumption
June 22, 2018 by Leave a Comment
Today Gidel announced a new compression IP and a renewed focus on compression and encryption algorithms for the HPC and Vision markets. The compression algorithm requires extremely low power, encoding more than 1 GB/sec utilizing just 1% of the FPGA, thus opening up new possibilities for data centers in particular. “Real-time compression capability provides a number of advantages in storage and efficiency,” notes Ofer Pravda, VP Marketing & Sales at Gidel. “Compressed data can be stored in real-time, as opposed to systems that store the raw data and then compress offline at a later date.”
