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An Introduction to High Performance Computing

In this video, Bill Jenkins from Intel presents and introduction to High Performance Computing. “This online training will provide a high-level introduction to high performance computing, the problem it solves and the vertical markets it solves it in. Rather than focusing on the step by step, this training will educate into the concepts and resources available to perform the data analytics process and even also discuss where accelerators can be used.”

How FPGAs Provide Versatile Acceleration for HPE Servers

In this video from SC18 in Dallas, Osama Sarfaraz from HPE describes how the company is using Intel FPGA’s to deliver Programmability, Flexibility, and Upgradability for HPC users. “The FPGA is designed to actually be configured by a customer or designer after manufacturing; hence it is “field-programmable.” An FPGA offers high I/O bandwidth plus a fine-grained, flexible and custom parallelism, allowing it to be programmed for many different types of workloads, including Big Data analytics, financial services and deep learning.”

Xilinx Steps Up with Alveo FPGA boards and Versal Adaptive Compute Acceleration Platform

Today FPGA maker Xilinx unveiled Versal, “the industry’s first adaptive compute acceleration platform (ACAP)”. The company also announced new Alveo FPGA cards, which the company claims can deliver “4X the performance of GPUs, 90X the performance of CPUs, plus unprecedented adaptability across workloads.” AMD, one of the Xilinx partners that is showcasing products based on the new Alveo boards, announced a server that will set a new world record for real-time AI inference processing, with a mind-boggling 30,000-images-per-second inference throughput.

Intel Beefs up FPGA Line

Today Intel introduced the Intel Programmable Acceleration Card (PAC) with Intel Stratix 10 SX FPGA. The card leverages the Acceleration Stack for Intel Xeon CPU with FPGAs, providing data center developers a robust platform to deploy FPGA-based accelerated workloads. 

Gidel Launches Lossless Compression IP that Reduces FPGA Power Consumption

Today Gidel announced a new compression IP and a renewed focus on compression and encryption algorithms for the HPC and Vision markets. The compression algorithm requires extremely low power, encoding more than 1 GB/sec utilizing just 1% of the FPGA, thus opening up new possibilities for data centers in particular. “Real-time compression capability provides a number of advantages in storage and efficiency,” notes Ofer Pravda, VP Marketing & Sales at Gidel. “Compressed data can be stored in real-time, as opposed to systems that store the raw data and then compress offline at a later date.”

Intel to Showcase AI and HPC Demos at ISC 2018

Today Intel released a sneak peek at their plans for ISC 2018 in Frankfurt. The company will showcase how it’s helping AI developers, data scientists and HPC programmers transform industries by tapping into HPC to power the AI solutions. “ISC brings together academic and commercial disciplines to share knowledge in the field of high performance computing. Intel’s presence at the event will include keynotes, sessions, and booth demos that will be focused on the future of HPC technology, including Artificial Intelligence (AI) and visualization.”

Call For Presentations: MVAPICH User Group Meeting (MUG 2018)

The MVAPICH User Group Meeting (MUG 2018) has issued its Call For Presentations. The event will take place from August 6-8 in Columbus, Ohio. “MUG aims to bring together MVAPICH2 users, researchers, developers, and system administrators to share their experience and knowledge and learn from each other. The event includes Keynote Talks, Invited Tutorials, Invited Talks, Contributed Presentations, Open MIC session, hands-on sessions  MVAPICH developers, etc.”

Unified Deep Learning Configurations and Emerging Applications

This is the final post in a five-part series from a report exploring the potential machine and a variety of computational approaches, including CPU, GPU and FGPA technologies. This article explores unified deep learning configurations and emerging applications. 

Unified Deep Learning with CPU, GPU and FPGA Technologies

Deep learning and complex machine learning has quickly become one of the most important computationally intensive applications for a wide variety of fields. Download the new paper — from Advanced Micro Devices Inc. (AMD) and Xilinx Inc. — that explores the challenges of deep learning training and inference, and discusses the benefits of a comprehensive approach for combining CPU, GPU, FPGA technologies, along with the appropriate software frameworks in a unified deep learning architecture.

FPGA Programming Made Easy

In the past, it was necessary to understand a complex programming language such as Verilog or VHDL, that was designed for a specific FPGA. “Using a familiar language such as OpenCL, developers can become more productive, sooner when deciding to use an FPGA for a specific purpose. OpenCL is portable and is designed to be used with almost any type of accelerator.”