Sign up for our newsletter and get the latest big data news and analysis.

Univ. of Buffalo’s Paul DesJardin Elected Fellow of ASME

Paul DesJardin of the University of Buffalo has been elected fellow of the American Society of Mechanical Engineers (ASME) in recognition of his exceptional achievements and contributions to the engineering profession. ASME fellows are conferred annually and fellow is the highest grade of membership. DesJardin, professor in the Department of Mechanical and Aerospace Engineering, School […]

Porting a Particle-in-Cell Code to Exascale Architectures

By Nils Heinonen on behalf of the Argonne Leadership Computing Facility As part of a series aimed at sharing best practices in preparing applications for Aurora, we highlight researchers’ efforts to optimize codes to run efficiently on graphics processing units. Take advantage of upgrades being made to high-level, non-machine-specific libraries and programming models Developed in […]

 Preparing for Exascale: ALCF’s Aurora Early Science Program and Visualizing Cancer’s Spread

Scientists are preparing a cancer modeling study to run on Argonne’s upcoming Aurora supercomputer before it goes online in 2022. The U.S. Department of Energy’s (DOE) Argonne National Laboratory will be home to one of the nation’s first exascale supercomputers – Aurora is scheduled to arrive in 2022. To prepare codes for the architecture and scale of […]

Meet the Frontier Exascale Supercomputer: How Big Is a Quintillion?

Are all comparisons so odious, really? Some can illuminate, some can awe. HPE-Cray has put out an infographic about its Frontier exascale supercomputer, the U.S.’s first, scheduled to be shipped to Oak Ridge National Laboratory later this year. It’s got interesting comparisons that shed light on how big a quintillion is. Make that 1.5 quintillion, […]

‘Intel Is Back’: Gelsinger Delivers Upbeat Update, Expanded Manufacturing in U.S., Europe

New Intel CEO Pat Gelsinger delivered an upbeat corporate update this afternoon in the form of a webinar that emphasized Intel’s integrated device manufacturing, “IDM.2.0” strategy for manufacturing and product development that combines the company’s internal network of factories with third-party outsourced capacity and new Intel foundries in the U.S. and Europe. “As I hope […]

Stop the Lab Worship: Commercial HPC is Sexy, Too

There’s a trend in the data storage world to call out a growing “divide” between HPC and enterprise storage. We believe that’s an oversimplification. What’s worse, it reinforces popular myths coursing through the HPC landscape that revel in what we call “lab worship” at the expense of more mainstream enterprise customers.  

SiPearl Says Rhea Exascale Chip Has Entered Accelerated Simulation Phase for 2022 Launch

SiPearl, the company designing the Rhea microprocessor for the European exascale supercomputer, announced it has passed a milestone before the chip’s scheduled 2022 launch. The company said it is moving into an “accelerated simulation phase” on the Veloce Strato hardware emulator from Siemens Digital Industries Software. SiPeal said the hardware emulation platform provides its chips […]

Ungaro Departs: New HPC Leadership at HPE and Dell as Companies Vie for Server Top Spot

HPE and Dell, engaged in a neck-and-neck struggle for superiority in HPC servers, also are engaged in a reshuffling of their HPC leadership teams that may reflect similar visions of HPC’s evolving position across IT. Last week, we reported on Dell’s newly installed HPC management group following the departure in early February of Thierry Pellegrino, […]

NERSC, ALCF, Codeplay Partner on SYCL GPU Compiler

The National Energy Research Scientific Computing Center (NERSC) at Lawrence Berkeley National Laboratory (LBNL) and Argonne Leadership Computing Facility (ALCF) are working with Codeplay Software to enhance the LLVM SYCL GPU compiler capabilities for Nvidia A100 GPUs. The collaboration is designed to help NERSC and ALCF users, along with the HPC community in general, produce […]

Spotting HPC and Exascale Bottlenecks with TAU CPU/GPU/MPI Profiler

Programmers cannot blindly guess which sections of their code might bottleneck performance. This problem is worsened when codes run across the variety of hardware platforms supported by the Exascale Computing Project (ECP). A section of code that runs well on one system might be a bottleneck on another system. Differing hardware execution models further compound the performance challenges that face application developers; these models can include the somewhat restricted SIMD (Single Instruction Multiple Data) and SIMT (Single Instruction Multiple Thread) computing for GPU models and the more complex and general MIMD (Multiple Instruction Multiple Data) for CPUs. New software programming models, such as Kokkos, also introduce multiple layers of abstraction and lambda functions that can hide or obscure the low-level execution details due to their complexity and anonymous nature. Differing memory systems inside a node and differences in the communications fabric that connect high-performance computing (HPC) nodes in a distributed supercomputer environment add even greater challenges in identifying performance bottlenecks during application performance analysis.