Mark Himelstein, chief technology officer at RISC-V International, joins us to discuss the latest developments with the RISC-V instruction set architecture and its growing community and footprint. Topics include: HPC use cases from sensors to supercomputer, achieving customization without loss of compatibility, AI and its impact on chips and systems, and the question on everyone’s mind: when will we see RISC-V in servers and supercomputers? Himelstein also looks at RISC-V’s design wins, including EuroHPC’s backing of R&D to develop HPC hardware and software based on RISC-V. You may also be interested in Shahin’s conversation with Mark in August 2020 to hear how things have evolved since then.
Bluespec Launches MCUX RISC-V Processor
June 27, 2023 by
Framingham, Mass. – June 27, 2023 – Bluespec Inc. today announced its new MCUX RISC-V processor designed to ease implementation of custom instructions and the addition of accelerators to FPGAs and ASICs. The MCUX is an extension of Bluespec’s MCU RISC-V processor family, which is targeted at ultra-low resource utilization on FPGAs. Bluespec said the […]
UK Startup VyperCore Says Its RISC-V Chip’s Memory Management Innovation Delivers 10X Performance Boost
May 4, 2023 by
A UK chip startup, VyperCore, says it has come up with a memory management scheme that does a software layer end-around and delivers as much as a 10x throughput improvement for high performance, general-purpose workloads without code modification. The company’s core insight, as described in a recent EE Times article: move “away from the processor’s […]
RISC-V Chip Maker SiFive Joins OpenMP Review Board
March 14, 2023 by
Beaverton, Oregon — March 14, 2023 — SiFive has joined the OpenMP Architecture Review Board (ARB), a group of hardware vendors, software vendors and research organizations, in creating the standard for the OpenMP shared-memory parallel programming model. SiFive is a RISC-V-based high-performance embedded systems platform company, delivering high-performance compute density for modern workloads. SiFive solutions are […]
RISC-V Summit China 2022 Announces Agenda
August 12, 2022 by
Shanghai, August 12, 2022 – The RISC-V Summit China 2022 (Aug. 24-26) today announced its 2022 agenda, including keynotes, tutorials, and technical presentations in English language and Chinese language editions. This year’s summit includes more than 80 tech talks, showcases, and tutorials and will include presentations in both Chinese and English. The RISC-V Summit brings together innovators, […]
RISC-V Announces First Specifications of 2022
June 21, 2022 by
Nuremberg, Germany – June 21, 2022 – RISC-V International, the open-design standards organization, announced its first four specification and extension approvals of 2022 – Efficient Trace for RISC-V (E-Trace), RISC-V Supervisor Binary Interface (SBI), RISC-V Unified Extensible Firmware Interface (UEFI) specifications, and the RISC-V Zmmul multiply-only extension. The news builds on momentum from 2021, in which 16 […]
SiFive and Intel Foundry Services Launch $1B Partnership for RISC-V Markets
February 7, 2022 by
SANTA CLARA, Calif., Feb. 7, 2022 — Intel today announced a $1 billion fund to support early-stage startups and established companies building disruptive technologies for the foundry ecosystem. A collaboration between Intel Capital and Intel Foundry Services (IFS), the fund will prioritize investments in capabilities that accelerate foundry customers’ time to market – spanning intellectual property (IP), software tools, […]
March 30: CHIPS Alliance and RISC-V International Invite the RISC-V Community to Update Unified Memory Architecture Standard
March 24, 2021 by
SAN FRANCISCO, March 24, 2020 – RISC-V International, a non-profit corporation controlled by its members to drive the adoption and implementation of the free and open RISC-V instruction set architecture (ISA), and CHIPS Alliance, a consortium advancing common and open hardware for interfaces, processors and systems, today announced a joint collaboration to update the OmniXtend Cache Coherency specification […]
3 RISC-V Forums Scheduled
March 17, 2021 by
The RISC-V Forum will hold three conferences starting next month that are free of charge to members and non-members and designed to provide deep-dive technical content for the RISC-V community The first conference, the Security Forum, will be held Wednesday, April 14 from 7-10am US Pacific Time. The agenda and registration can be found here. The second event, […]
RISC-V International Unveils Fast Track Architecture Extension Process and Ratifies ZiHintPause Extension
February 23, 2021 by
Zurich – Feb. 23, 2021 – RISC-V International, a non-profit corporation controlled by its members to drive the adoption and implementation of the free and open RISC-V instruction set architecture (ISA), unveiled its Fast Track Architecture Extension Process (Fast Track) that streamlines the ratification of small architecture extensions. ZiHintPause is the first extension to be ratified under […]
