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March 30: CHIPS Alliance and RISC-V International Invite the RISC-V Community to Update Unified Memory Architecture Standard

SAN FRANCISCO, March 24, 2020 – RISC-V International, a non-profit corporation controlled by its members to drive the adoption and implementation of the free and open RISC-V instruction set architecture (ISA), and CHIPS Alliance, a consortium advancing common and open hardware for interfaces, processors and systems, today announced a joint collaboration to update the OmniXtend Cache Coherency specification […]

3 RISC-V Forums Scheduled

The RISC-V Forum will hold three conferences starting next month that are free of charge to members and non-members and designed to provide deep-dive technical content for  the RISC-V community The first conference, the Security Forum, will be held Wednesday, April 14 from 7-10am US Pacific Time. The agenda and registration can be found here. The second event, […]

RISC-V International Unveils Fast Track Architecture Extension Process and Ratifies ZiHintPause Extension

Zurich – Feb. 23, 2021 – RISC-V International, a non-profit corporation controlled by its members to drive the adoption and implementation of the free and open RISC-V instruction set architecture (ISA), unveiled its Fast Track Architecture Extension Process (Fast Track) that streamlines the ratification of small architecture extensions. ZiHintPause is the first extension to be ratified under […]

Cobham Gaisler and fentISS Deepen Collaboration around RISC-V

Valencia, Spain — Cobham Gaisler, a leading space design center of Cobham Advanced Electronic Solutions (CAES), announced that fent Innovative Software Solutions (fentISS), a developer of software solutions specifically designed for critical real-time embedded partitioned systems, has agreed to mutually promote flagship products NOEL-V and LEON5 processors and the XtratuM Next Generation (XNG) hypervisor. Promoting […]

Radio Free HPC: RISC-V Deep Dive, CTO Interview

In this special edition of Radio Free HPC, we interview Mark Himelstein, RISC-V International Chief Technical Officer, looking at RISC-V from all angles, discussing how the open source ISA is used today and how it might be used tomorrow. And there’s a lot to consider. The European Processor Initiative has selected RISC-V as their accelerator of choice for their first exascale machines. The first system is expected in the 2022-2023 timeframe and will couple RISC-V accelerators with Arm processors.

Radio Free HPC: SiFive’s Big Score, Will Nvidia Buy Arm?

We start out with our personal pledge that all of our content is new and not pre-recorded. That’s our gift to you – no recycled, reused or Amazon Renewed content.  Jumping into our first topic, Risc-V IP and silicon purveyor SiFive earned a $61 million investment from a group of high-end investors including SK Hynix, Qualcomm […]

Video: RISC-V momentum around the world, from edge to HPC

In this keynote talk from the 2020 HiPEAC conference, RISC-V Foundation Chief Executive Calista Redmond explains how the RISC-V open-source instruction set architecture is gathering momentum around the world, finding applications across the compute continuum from edge to high-performance computing. “The RISC-V ecosystem is poised to significantly grow over the next five years. Semico Research predicts that the market will consume a total of 62.4 billion RISC-V central processing unit (CPU) cores by 2025!”

Exascale in Europe

Europe has developed a strategy for exascale computing, through partnerships and collaboration of European HPC vendors, academic institutions and HPC centers. It aims to deliver exascale-class systems and place the continent in the top three powers for supercomputing and science and industry using HPC. “It is a major step forward for Europe to reach the next level of computing capacity; it will help us to advance in future-oriented technologies, like the Internet of Things (Iot), AI, robotics and data analytics.”

2020 Predictions from Radio Free HPC

In this podcast, the Radio Free HPC team lays out their tech predictions for 2020. “Henry predicts that we’ll see a RISC-V based supercomputer on the TOP500 list by the end of 2020 – gutsy call on that. This is a double down on a bet that Dan and Henry have, so he’s reinforcing his position. Dan also sees 2020 as the “Year of the FPGA.”

2020 HiPEAC Conference to Showcase European Computing Technologies

The 2020 HiPEAC conference will kick off next week in Bologna to showcase the innovative made-in-Europe technologies driving computing systems from the edge to the cloud. This year, the conference will dive into radical new developments in European processor technology, including open source hardware, while building on HiPEAC’s long-established reputation for cutting-edge research into heterogeneous architectures, cross-cutting artificial intelligence themes, security and more.