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RISC-V Summit China 2022 Announces Agenda

Shanghai, August 12, 2022 – The RISC-V Summit China 2022 (Aug. 24-26) today announced its 2022 agenda, including keynotes, tutorials, and technical presentations in English language and Chinese language editions. This year’s summit includes more than 80 tech talks, showcases, and tutorials and will include presentations in both Chinese and English. The RISC-V Summit brings together innovators, […]

RISC-V Announces First Specifications of 2022

Nuremberg, Germany – June 21, 2022 – RISC-V International, the open-design standards organization, announced its first four specification and extension approvals of 2022 – Efficient Trace for RISC-V (E-Trace), RISC-V Supervisor Binary Interface (SBI), RISC-V Unified Extensible Firmware Interface (UEFI) specifications, and the RISC-V Zmmul multiply-only extension. The news builds on momentum from 2021, in which 16 […]

SiFive and Intel Foundry Services Launch $1B Partnership for RISC-V Markets

SANTA CLARA, Calif., Feb. 7, 2022 — Intel today announced a $1 billion fund to support early-stage startups and established companies building disruptive technologies for the foundry ecosystem. A collaboration between Intel Capital and Intel Foundry Services (IFS), the fund will prioritize investments in capabilities that accelerate foundry customers’ time to market – spanning intellectual property (IP), software tools, […]

March 30: CHIPS Alliance and RISC-V International Invite the RISC-V Community to Update Unified Memory Architecture Standard

SAN FRANCISCO, March 24, 2020 – RISC-V International, a non-profit corporation controlled by its members to drive the adoption and implementation of the free and open RISC-V instruction set architecture (ISA), and CHIPS Alliance, a consortium advancing common and open hardware for interfaces, processors and systems, today announced a joint collaboration to update the OmniXtend Cache Coherency specification […]

3 RISC-V Forums Scheduled

The RISC-V Forum will hold three conferences starting next month that are free of charge to members and non-members and designed to provide deep-dive technical content for  the RISC-V community The first conference, the Security Forum, will be held Wednesday, April 14 from 7-10am US Pacific Time. The agenda and registration can be found here. The second event, […]

RISC-V International Unveils Fast Track Architecture Extension Process and Ratifies ZiHintPause Extension

Zurich – Feb. 23, 2021 – RISC-V International, a non-profit corporation controlled by its members to drive the adoption and implementation of the free and open RISC-V instruction set architecture (ISA), unveiled its Fast Track Architecture Extension Process (Fast Track) that streamlines the ratification of small architecture extensions. ZiHintPause is the first extension to be ratified under […]

Cobham Gaisler and fentISS Deepen Collaboration around RISC-V

Valencia, Spain — Cobham Gaisler, a leading space design center of Cobham Advanced Electronic Solutions (CAES), announced that fent Innovative Software Solutions (fentISS), a developer of software solutions specifically designed for critical real-time embedded partitioned systems, has agreed to mutually promote flagship products NOEL-V and LEON5 processors and the XtratuM Next Generation (XNG) hypervisor. Promoting […]

Radio Free HPC: RISC-V Deep Dive, CTO Interview

In this special edition of Radio Free HPC, we interview Mark Himelstein, RISC-V International Chief Technical Officer, looking at RISC-V from all angles, discussing how the open source ISA is used today and how it might be used tomorrow. And there’s a lot to consider. The European Processor Initiative has selected RISC-V as their accelerator of choice for their first exascale machines. The first system is expected in the 2022-2023 timeframe and will couple RISC-V accelerators with Arm processors.

Radio Free HPC: SiFive’s Big Score, Will Nvidia Buy Arm?

We start out with our personal pledge that all of our content is new and not pre-recorded. That’s our gift to you – no recycled, reused or Amazon Renewed content.  Jumping into our first topic, Risc-V IP and silicon purveyor SiFive earned a $61 million investment from a group of high-end investors including SK Hynix, Qualcomm […]

Video: RISC-V momentum around the world, from edge to HPC

In this keynote talk from the 2020 HiPEAC conference, RISC-V Foundation Chief Executive Calista Redmond explains how the RISC-V open-source instruction set architecture is gathering momentum around the world, finding applications across the compute continuum from edge to high-performance computing. “The RISC-V ecosystem is poised to significantly grow over the next five years. Semico Research predicts that the market will consume a total of 62.4 billion RISC-V central processing unit (CPU) cores by 2025!”