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2020 Predictions from Radio Free HPC

In this podcast, the Radio Free HPC team lays out their tech predictions for 2020. “Henry predicts that we’ll see a RISC-V based supercomputer on the TOP500 list by the end of 2020 – gutsy call on that. This is a double down on a bet that Dan and Henry have, so he’s reinforcing his position. Dan also sees 2020 as the “Year of the FPGA.”

2020 HiPEAC Conference to Showcase European Computing Technologies

The 2020 HiPEAC conference will kick off next week in Bologna to showcase the innovative made-in-Europe technologies driving computing systems from the edge to the cloud. This year, the conference will dive into radical new developments in European processor technology, including open source hardware, while building on HiPEAC’s long-established reputation for cutting-edge research into heterogeneous architectures, cross-cutting artificial intelligence themes, security and more.

Joe Landman on How the Cloud is Changing HPC

In this special guest feature, Joe Landman from Scalability.org writes that the move to cloud-based HPC is having some unexpected effects on the industry. “When you purchase a cloud HPC product, you can achieve productivity in time scales measurable in hours to days, where previously weeks to months was common. It cannot be overstated how important this is.”

RISC-V Lagarto is First Open Source Chip Developed in Spain

The Barcelona Supercomputing Center has coordinated the manufacture of the first open source chip developed in Spain. “Lagarto is an important step in the search of the BSC, led by the center’s director, Mateo Valero, to develop European computing technology. This project is based on the premise that the instruction set of the future processors must be open source to ensure transparency and minimize dependence.”

De-RISC Computing Platform for Space will be built with made-in-Europe Technology

A new European project called De-RISC is preparing a hardware-software platform based on RISC-V for the space and aviation market. Combining a multicore system-on-chip by leading space solutions provider Cobham Gaisler with fentISS’ space-qualified XtratuM hypervisor, De-RISC will create a market-ready platform to power future space and aeronautical applications with made-in-Europe technology. “The use of RISC-V will also help to future-proof the platform, thanks to an ever-increasing support for the open-source instruction set architecture (ISA), at a time when the proprietary PowerPC and SPARC architectures traditionally used in aviation and space systems are experiencing a loss of momentum. As a result, the space industry is not able to leverage software from the commercial domains, fueling a need to shift to architectures present in higher volume commercial markets. The final platform will be portable to other architectures, and it will also provide superior fault tolerance.”

New LOCA Facility to Develop Open Computer Architectures at BSC in Barcelona

Today the Barcelona Supercomputing Center (BSC) announced the European Laboratory for Open Computer Architecture (LOCA). LOCA’s mission is to design and develop energy efficient and high performance chips, based on open architectures like RISC-V, OpenPOWER, and MIPS, in Europe, for use within future exascale supercomputers and other high performance domains. ““We are launching it with great conviction, because it is another step in our philosophy of paving the way for the creation of European HPC architectures.”

European Processor Initiative Reaches Important Milestones in First Year

The European Processor Initiative (EPI) has announced the completion of important milestones in its first year. “The first-generation chip family, named Rhea, will include Arm ZEUS architecture general purpose cores and prototypes of high energy-efficient accelerator tiles: RISC-V based (EPAC), Multi-Purpose Processing Array (MPPA), embedded FPGA (eFPGA) and cryptography HW engine. First Rhea chips will be fabricated in N6 technology aiming at the highest processing capabilities and energy efficiency.”

Podcast: RISC-V CEO Sees Bright Global Future for Open Source CPUs

In this podcast, the Radio Free HPC team catches up with Calista Redmond, CEO of RISC-V. “RISC-V can be used for light weight tasks such as embedded processing but, on the other hand, is also going to be utilized as the system accelerator for the European Exascale initiative boxes. That’s some serious flexibility.”

How the European Processor Initiative is Leveraging RISC-V for the Future of Supercomputing

In this special guest feature, Calista Redmond writes that the European Processor Initiative is designing an HPC accelerator based on RISC-V. “The accelerator will be designed for high throughput and power efficiency within the general purpose processor (GPP) chip. The EPI explains that using RISC-V enables the program to leverage “open source resources at [the] hardware architecture level and software level, as well as ensuring independence from non-European patented computing technologies.”

Calista Redmond named CEO of RISC-V Foundation

Today the RISC-V Foundation announced that Calista Redmond has been appointed Chief Executive Officer (CEO), effective immediately. I’ve always understood the potential short- and long-term impact of the RISC-V license-free ISA on the open source community. Having spent a lot of my career working in the open source ecosystem, I’m excited to help RISC-V grow and deliver on the Foundation’s mission of paving the way for the next 50 years of computing design and innovation,” said Redmond, CEO of the RISC-V Foundation.”